VDD = 2.7 V to 3.6 V, or 4.75" />
參數(shù)資料
型號: EVAL-AD7746EBZ
廠商: Analog Devices Inc
文件頁數(shù): 24/28頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD7746
標(biāo)準(zhǔn)包裝: 1
傳感器類型: 觸摸,電容式
接口: I²C
電源電壓: 2.7 V ~ 5.25 V
嵌入式:
已供物品: 板,纜線,CD
已用 IC / 零件: AD7746
產(chǎn)品目錄頁面: 781 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: AD7746ARUZ-ND - IC CONV 2CH CAP TO DGTL 16-TSSOP
AD7746ARUZ-REEL7-ND - IC CONV 2CH CAP TO DGTL 16-TSSOP
AD7746ARUZ-REEL-ND - IC CONV 2CH CAP TO DGTL 16-TSSOP
AD7745/AD7746
Rev. 0| Page 5 of 28
TIMING SPECIFICATIONS
VDD = 2.7 V to 3.6 V, or 4.75 V to 5.25 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; –40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SERIAL INTERFACE1, 2
SCL Frequency
0
400
kHz
SCL High Pulse Width, tHIGH
0.6
s
SCL Low Pulse Width, tLOW
1.3
s
SCL, SDA Rise Time, tR
0.3
s
SCL, SDA Fall Time, tF
0.3
s
Hold Time (Start Condition), tHD;STA
0.6
s
After this period, the first clock is generated
Set-Up Time (Start Condition), tSU;STA
0.6
s
Relevant for repeated start condition
Data Set-Up Time, tSU;DAT
0.25
s
VDD ≥ 3.0 V
Data Set-Up Time, tSU;DAT
0.35
s
VDD < 3.0 V
Set-Up Time (Stop Condition), tSU;STO
0.6
s
Data Hold Time, tHD;DAT (Master)
0
s
Bus-Free Time (Between Stop and Start Condition, tBUF)
1.3
s
1 Sample tested during initial release to ensure compliance.
2 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
P
S
tLOW
tR
tF
tHD:STA
tHD:DAT
tSU:DAT
tSU:STA
tHD:STA
tSU:STO
tHIGH
SCL
PS
SDA
tBUF
05468-003
Figure 3. Serial Interface Timing Diagram
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