參數(shù)資料
型號： EVAL-AD7706EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 28/44頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD7706
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 16
采樣率（每秒）： 500
數(shù)據(jù)接口： 串行
輸入范圍： 0 ~ 5.25 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 6.5mW @ 500SPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7706
已供物品： 板，CD
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AD7705/AD7706
Rev. C | Page 34 of 44
MICROCOMPUTER/MICROPROCESSOR
INTERFACING
The flexible serial interface of the AD7705/AD7706 allows easy
interfacing to most microcomputers and microprocessors.
The flowchart in Figure 21 outlines the sequence to follow
when interfacing a microcontroller or microprocessor to the
AD7705/AD7706. Figure 22 through Figure 24 show typical
interface circuits.
The serial interface is capable of operating from three wires and
is compatible with SPI interface protocols. The 3-wire operation
makes these parts ideal for an isolated system in which minimizing
the number of interface lines minimizes the number of
opto-isolators required in the system. The serial clock input is a
Schmitt-triggered input to accommodate slow edges from opto-
couplers. The rise and fall times of other digital inputs to the
AD7705/AD7706 should be no longer than 1 μs.
Most of the registers on the AD7705/AD7706 are 8-bit registers,
which facilitates easy interfacing to the 8-bit serial ports of micro-
controllers. The data register on the AD7705/AD7706 is 16 bits,
and the offset and gain registers are 24-bit registers, but data
transfers to these registers can consist of multiple 8-bit transfers
to the serial port of the microcontroller. DSP processors and
microprocessors generally transfer 16 bits of data in a serial data
operation. Some of these processors, such as the ADSP-2105,
have the facility to program the number of cycles in a serial
transfer. This allows the user to tailor the number of bits in any
transfer to match the length of the required register in the
AD7705/AD7706.
Because some registers on the AD7705/AD7706 are only 8 bits
long, successive write operations to two of these registers can be
handled as a single 16-bit data transfer. For example, to update
the setup register, the processor must write to the communication
register to indicate that the next operation is a write to the setup
register, and then write 8 bits to the setup register. This can be
done in a single 16-bit transfer, because once the eight serial
clocks of the write operation to the communication register are
complete, the part immediately sets up for a write operation to
the setup register.
AD7705/AD7706-to-68HC11 Interface
Figure 22 shows an interface between the AD7705/AD7706 and
the 68HC11 microcontroller. The diagram shows the minimum
(3-wire) interface with CS on the AD7705/AD7706 hardwired
low. In this scheme, the DRDY bit of the communication register
is monitored to determine when the data register is updated. An
alternative scheme, which increases the number of interface lines
to four, is to monitor the DRDY output line from the AD7705/
AD7706. Monitoring the DRDY line can be done in two ways.
First, DRDY can be connected to a 68HC11 port bit (such as
PC0) that is configured as an input. This port bit is then polled
to determine the status of DRDY.
The second scheme is to use an interrupt-driven system, in
which case the DRDY output is connected to the IRQ input of
the 68HC11. For interfaces that require control of the CS input
on the AD7705/AD7706, a port bit of the 68HC11 (such as
PC1) that is configured as an output can be used to drive the CS
input.
SS
SCK
MISO
MOSI
68HC11
RESET
SCLK
DOUT
DIN
CS
AD7705/AD7706
VDD
01166-022
Figure 22. AD7705/AD7706-to-68HC11 Interface
The 68HC11 is configured in master mode with its CPOL and
CPHA bits set to Logic 1. When the 68HC11 is configured like
this, its SCLK line idles high between data transfers. The AD7705/
AD7706 are not capable of a full duplex operation. If the AD7705/
AD7706 are configured for a write operation, no data appears
on the DOUT lines, even when the SCLK input is active.
Similarly, if the AD7705/AD7706 are configured for a read
operation, data presented to the part on the DIN line is ignored,
even when SCLK is active.
Coding for an interface between the 68HC11 and the AD7705/
AD7706 is given in the C Code for Interfacing AD7705 to
68HC11 section. In this example, the DRDY output line of the
AD7705 is connected to the PC0 port bit of the 68HC11 and is
polled to determine its status.
P3.0
P3.1
8XC51
RESET
SCLK
DOUT
DIN
CS
AD7705/AD7706
VDD
01166-023
Figure 23. AD7705/AD7706-to-8XC51 Interface
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