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參數(shù)資料
| 型號： | EVAL-AD7699EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7699 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 輸入范圍： | 0 ~ Vdd |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 28mW @ 500kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7699 |
| 已供物品： | 板 |
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Data Sheet
AD7699
Rev.
| Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
VDD
2
REF
3
REFIN
4
GND
5
GND
13 SCK
14 SDO
15 VIO
12 DIN
11 CNV
6
IN
4
7
IN
5
8
IN
6
0
1
C
O
M
9
IN
7
81
IN
2
91
IN
3
02
V
D
7
1
IN
1
61
IN
0
TOP VIEW
(Not to Scale)
AD7699
07
35
4-
0
04
NOTES
1. THE EXPOSED PADDLE IS NOT CONNECTED INTERNALLY.
FOR INCREASED RELIABILITY OF THE SOLDER JOINTS,
IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO
THE GND PLANE.
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Type1
1, 20
VDD
P
Power Supply. Nominally 4.5 to 5.5 V and should be decoupled with 10 μF and 100 nF capacitors.
2
REF
AI/O
Reference Input/Output. See the Voltage Reference Output/Input section.
When the internal reference is enabled, this pin produces 4.096 V. When the internal reference is disabled
and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin
(VDD – 0.5 V maximum) useful when using low cost, low power references.
For improved drift performance, connect a precision reference to REF (0.5 V to VDD).
For any reference method, this pin needs decoupling with an external 10 μF capacitor connected as
close to REF as possible. See the Reference Decoupling section.
3
REFIN
AI/O
Internal Reference Output/Reference Buffer Input. See the Voltage Reference Output/Input section.
When using the internal reference, the internal unbuffered reference voltage is present and needs
decoupling with a 0.1 μF capacitor.
When using the internal reference buffer, apply a source between 0.5 V and 4.096 V that is buffered to
the REF pin as previously described.
4, 5
GND
P
Power Supply Ground.
6 to 9
IN4 to IN7
AI
Analog Input Channel 4, Analog Input Channel 5, Analog Input Channel 6, and Analog Input Channel 7.
10
COM
AI
Common Channel Input. All input channels, IN[7:0], can be referenced to a common-mode point of 0 V
or VREF/2 V.
11
CNV
DI
Conversion Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held
high, the busy indictor is enabled.
12
DIN
DI
Data Input. This input is used for writing to the 14-bit configuration register. The configuration register
can be written to during and after conversion.
13
SCK
DI
Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an
MSB first fashion.
14
SDO
DO
Serial Data Output. The conversion result is output on this pin and synchronized to SCK. In unipolar
modes, conversion results are straight binary; in bipolar modes, conversion results are twos
complement.
15
VIO
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V,
3 V, or 5 V).
16 to 19
IN0 to IN3
AI
Analog Input Channel 0, Analog Input Channel 1, Analog Input Channel 2, and Analog Input Channel 3.
21 (EPAD)
Exposed
Paddle
(EPAD)
The exposed paddle is not connected internally. For increased reliability of the solder joints, it is
recommended that the pad be soldered to the GND plane.
1AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power.
B
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