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參數資料
| 型號： | EVAL-AD7690SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 14/24頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7690 |
| 標準包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數量： | 1 |
| 位數： | 18 |
| 采樣率（每秒）： | 400k |
| 數據接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 輸入范圍： | ±VREF |
| 在以下條件下的電源（標準）： | 17mW @ 100kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7690 |
| 已供物品： | 板 |
AD7690
Rev. B | Page 21 of 24
CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7690s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7690s is shown in
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7690 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 18 × N clocks are required to
read back the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and consequently more AD7690s in the chain, provided the
digital host has an acceptable hold time. The maximum conversion
rate may be reduced due to the total readback time.
CLK
CONVERT
DATA IN
DIGITAL HOST
CNV
SCK
SDO
SDI
CNV
SCK
SDO
SDI
AD7690
B
AD7690
A
05
79
2
-01
9
Figure 42. Chain Mode Without Busy Indicator Connection Diagram
SDOA = SDIB
DA17
DA16
DA15
SCK
12
3
34
35
36
tSSDISCK
tHSDISCK
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV
DA1
16
17
tSCK
tSCKL
tSCKH
DA0
19
20
18
SDIA = 0
SDOB
DB17
DB16
DB15
DA1
DB1DB0DA17
DA16
tHSDO
tDSDO
tSSCKCNV
tHSCKCNV
DA0
05
79
2-
0
20
Figure 43. Chain Mode Without Busy Indicator Serial Interface Timing
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