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參數(shù)資料
| 型號(hào)： | EVAL-AD7687CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 27/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7687 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±VREF |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 4mW @ 5V，100kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7687 |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | AD7687BCPZRL7DKR-ND - IC ADC 16BIT SAR 250KSPS 10LFCSP AD7687BCPZRL7CT-ND - IC ADC 16BIT SAR 250KSPS 10LFCSP AD7687BCPZRL7TR-ND - IC ADC 16BIT SAR 250KSPS 10LFCSP AD7687BCPZRL-ND - IC ADC 16BIT SAR 250KSPS 10LFCSP AD7687BRMZ-ND - IC ADC 16BIT 250KSPS 10-MSOP AD7687BRMZRL7-ND - IC ADC 16BIT 250KSPS 10MSOP |
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AD7687
Data Sheet
Rev. B | Page 8 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
02972-
005
REF
1
VDD
2
IN+
3
IN–
4
GND
5
VIO
10
SDI
9
SCK
8
SDO
7
CNV
6
AD7687
TOP VIEW
(Not to Scale)
Figure 5. 10-Lead MSOP Pin Configuration
02
972
-0
06
1
REF
2
VDD
3
IN+
4
IN–
5
GND
10 VIO
9SDI
8SCK
7SDO
6 CNV
NOTES
1. FOR THE LFCSP PACKAGE ONLY,
THE EXPOSED PADDLE MUST BE
CONNECTED TO GND.
TOP VIEW
(Not to Scale)
AD7687
Figure 6. 10-Lead QFN (LFCSP) Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Function
1
REF
AI
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should
be decoupled closely to the pin with a 10 μF capacitor.
2
VDD
P
Power Supply.
3
IN+
AI
Differential Positive Analog Input.
4
IN
AI
Differential Negative Analog Input.
5
GND
P
Power Supply Ground.
6
CNV
DI
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode, chain or CS. In CS mode, it enables the SDO pin when low. In chain mode, the
data should be read when CNV is high.
7
SDO
DO
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8
SCK
DI
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9
SDI
DI
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to
daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on
SDI is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY
indicator feature is enabled.
10
VIO
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V,
or 5 V).
EPAD
N/A
For the LFCSP package only, the exposed paddle must be connected to GND.
1AI = Analog Input, DI = Digital Input, DO = Digital Output, P = Power, and N/A = not applicable.
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