t3 BUSY CS, RD CNVST SYNC SCLK SDOUT 12 3 14 15 16 D15 D14 D2 D1 D0 X EXT/ INT = 0 RD" />
參數(shù)資料
型號(hào): EVAL-AD7675CBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 7/20頁(yè)
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD7675
標(biāo)準(zhǔn)包裝: 1
系列: PulSAR®
ADC 的數(shù)量: 1
位數(shù): 16
采樣率(每秒): 100k
數(shù)據(jù)接口: 串行,并聯(lián)
輸入范圍: ±VREF
在以下條件下的電源(標(biāo)準(zhǔn)): 17mW @ 100kSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD7675
已供物品:
相關(guān)產(chǎn)品: AD7675ACPZRL-ND - IC ADC 16BIT SAR 100KSPS 48LFCSP
AD7675ACPZ-ND - IC ADC 16BIT SAR 100KSPS 48LFCSP
AD7675ASTZ-ND - IC ADC 16BIT DIFF INP 48LQFP
AD7675ASTZRL-ND - IC ADC 16BIT DIFF INP 48LQFP
REV. A
AD7675
–15–
t3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
12
3
14
15
16
D15
D14
D2
D1
D0
X
EXT/
INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t14
t20
t15
t16
t22
t23
t29
t28
t18
t19
t21
t30
t25
t24
t26
t27
Figure 17. Master Serial Data Timing for Reading (Read after Convert)
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
D15
D14
D2
D1
D0
X
12
3
14
15
16
BUSY
SYNC
SCLK
SDOUT
CS, RD
CNVST
t3
t1
t17
t14
t15
t19
t20
t21
t16
t22
t23
t24
t27
t26
t25
t18
EXT/
INT = 0
Figure 18. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
SERIAL INTERFACE
The AD7675 is configured to use the serial interface when the
SER/
PAR is held high. The AD7675 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin.
MASTER SERIAL INTERFACE
Internal Clock
The AD7675 is configured to generate and provide the serial
data clock SCLK when the EXT/
INT pin is held low. The AD7675
also generates a SYNC signal to indicate to the host when the
serial data is valid. The serial clock SCLK and the SYNC signal
can be inverted if desired. The output data is valid on both the
rising and falling edge of the data clock. Depending on RDC/
SDIN input, the data can be read after each conversion, or
during the following conversion. Figure 17 and Figure 18 show
the detailed timing diagrams of these two modes.
Usually, because the AD7675 has a longer acquisition phase
than the conversion phase, the data is read immediately after
conversion. That makes the mode master, read after conversion,
the most recommended serial mode when it can be used.
相關(guān)PDF資料
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P1022DS-PA BOARD REFERENCE DESIGN P1022
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