參數(shù)資料
型號(hào)： EVAL-AD7656CBZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 5/32頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD7656
標(biāo)準(zhǔn)包裝： 1
系列： iCMOS®
ADC 的數(shù)量： 6
位數(shù)： 16
采樣率（每秒）： 250k
數(shù)據(jù)接口： 串行，并聯(lián)
輸入范圍： ±4 x VREF
在以下條件下的電源（標(biāo)準(zhǔn)）： 140mW @ 250kSPS & 5V
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7656
已供物品： 板，CD
產(chǎn)品目錄頁(yè)面： 778 (CN2011-ZH PDF)
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Data Sheet
AD7656/AD7657/AD7658
Rev. D | Page 13 of 32
Pin No.
Mnemonic
Description
7
DB8/DOUT A
Data Bit 8/Serial Data Output A. When SER/PAR = 0, this pin acts as a three-state parallel digital
output pin. When SER/PAR = 1 and SEL A = 1, this pin takes on its DOUT A function and outputs
serial conversion data.
6
DB9/DOUT B
Data Bit 9/Serial Data Output B. When SER/PAR = 0, this pin acts as a three-state parallel digital
output pin. When SER/PAR = 1 and SEL B = 1, this pin takes on its DOUT B function and outputs
serial conversion data. This configures the serial interface to have two DOUT output lines.
5
DB10/DOUT C
Data Bit 10/Serial Data Output C. When SER/PAR = 0, this pin acts as a three-state parallel digital
output pin. When SER/PAR = 1 and SEL C = 1, this pin takes on its DOUT C function and outputs
serial conversion data. This configures the serial interface to have three DOUT output lines.
4
DB11
Data Bit 11/Digital Ground. When SER/PAR = 0, this pin acts as a three-state parallel digital output
pin. When SER/PAR = 1, this pin should be tied to DGND.
3, 2, 64
DB12, DB13, DB15
Data Bit 12, Data Bit 13, Data Bit 15. When SER/PAR = 0, these pins act as three-state parallel digital
input/output pins. When CS and RD are low, these pins are used to output the conversion result.
When CS and WR are low, these pins are used to write to the control register. When SER/PAR = 1,
these pins should be tied to DGND. For the AD7657, DB15 contains a leading zero. For the AD7658,
DB15, DB13, and DB12 contain leading zeros.
1
DB14/REFBUFEN/DIS
Data Bit 14/REFBUF Enable/Disable. When SER/PAR = 0, this pin acts as a three-state digital input/
output pin. For the AD7657/AD7658, DB14 contains a leading zero. When SER/PAR = 1, this pin can be
used to enable or disable the internal reference buffers.
28
RESET
Reset Input. When set to logic high, this pin resets the AD7656/AD7657/AD7658. The current
conversion, if any, is aborted. The internal register is set to all 0s. In hardware mode, the
AD7656/AD7657/AD7658 are configured depending on the logic levels on the hardware select pins.
In all modes, the parts should receive a RESET pulse after power-up. The reset high pulse should be
typically 100 ns wide. After the RESET pulse, the AD7656/AD7657/AD7658 needs to see a valid
CONVST pulse to initiate a conversion; this should consist of a high-to-low CONVST edge followed
by a low-to-high CONVST edge. The CONVST signal should be high during the RESET pulse.
27
RANGE
Analog Input Range Selection. Logic input. The logic level on this pin determines the input range of
the analog input channels. When this pin is Logic 1 at the falling edge of BUSY, the range for the
next conversion is ±2 × VREF. When this pin is Logic 0 at the falling edge of BUSY, the range for the
next conversion is ±4 × VREF. In hardware select mode, the RANGE pin is checked on the falling edge
of BUSY. In software mode (H/S SEL = 1), the RANGE pin can be tied to DGND and the input range is
determined by the RNGA, RNGB, and RNGC bits in the control register.
31
VDD
Positive Power Supply Voltage. This is the positive supply voltage for the analog input section, and
10 F and 100 nF decoupling capacitors should be placed on the VDD pin.
30
VSS
Negative Power Supply Voltage. This is the negative supply voltage for the analog input section, and
10 F and 100 nF decoupling capacitors should be placed on the VSS pin.
24
STBY
Standby Mode Input. This pin is used to put all six on-chip ADCs into standby mode. The STBY pin is
high for normal operation and low for standby operation.
62
H/S SEL
Hardware/Software Select Input. Logic input. When H/S SEL = 0, the AD7656/AD7657/AD7658
operate in hardware select mode, and the ADC pairs to be simultaneously sampled are selected
by the CONVST pins. When H/S SEL = 1, the ADC pairs to be sampled simultaneously are selected by
writing to the control register. In serial mode, CONVST A is used to initiate conversions on the
selected ADC pairs.
29
W/B
Word/Byte Input. When this pin is logic low, data can be transferred to and from the AD7656/AD7657/
AD7658 using the parallel data lines DB[15:0]. When this pin is logic high, byte mode is enabled. In this
mode, data is transferred using data lines DB[15:8] and DB[7] takes on its HBEN function. To obtain the
16-bit conversion result, 2-byte reads are required. In serial mode, this pin should be tied to DGND.
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