參數(shù)資料
型號: EVAL-AD7650CBZ
廠商: Analog Devices Inc
文件頁數(shù): 9/20頁
文件大小: 0K
描述: BOARD EVALUATION FOR AD7650
標準包裝: 1
ADC 的數(shù)量: 1
位數(shù): 16
采樣率(每秒): 570k
數(shù)據(jù)接口: 串行,并聯(lián)
輸入范圍: ±VREF
在以下條件下的電源(標準): 150mW @ 570kSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD7650
已供物品:
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REV. 0
–17–
AD7650
MICROPROCESSOR INTERFACING
The AD7650 is ideally suited for traditional dc measurement appli-
cations supporting a microprocessor, and ac signal processing
applications interfacing to a digital signal processor. The AD7650
is designed to interface either with a parallel 16-bit-wide interface or
with a general-purpose serial port or I/O ports on a microcontroller.
A variety of external buffers can be used with the AD7650 to
prevent digital noise from coupling into the ADC. The following
sections illustrate the use of the AD7650 with an SPI-equipped
microcontroller, the ADSP-21065L and ADSP-218x signal
processors.
SPI Interface (MC68HC11)
Figure 18 shows an interface diagram between the AD7650 and an
SPI-equipped microcontroller like the MC68HC11. To accom-
modate the slower speed of the microcontroller, the AD7650 acts
as a slave device and data must be read after conversion. This mode
allows also the “daisy chain” feature.
The convert command could be initiated in response to an internal
timer interrupt. The reading of output data, one byte at a time,
if necessary, could be initiated in response to the end-of-conversion
signal (BUSY going low) using to an interrupt line of the
microcontroller. The Serial Peripheral Interface (SPI) on the
MC68HC11 is configured for master mode (MSTR = 1), Clock
Polarity Bit (CPOL) = 0, Clock Phase Bit (CPHA) = 1 and SPI
Interrupt Enable (SPIE = 1) by writing to the SPI Control Reg-
ister (SPCR). The IRQ is configured for edge-sensitive-only
operation (IRQE = 1 in OPTION register).
IRQ
MC68HC11
*
CNVST
AD7650*
CS
BUSY
MISO/SDI
SCK
I/O PORT
SDOUT
SCLK
RD
INVSCLK
EXT/
INT
SER/
PAR
DVDD
*ADDITIONAL PINS OMITTED FOR CLARITY
OVDD
Figure 18. Interfacing the AD7650 to SPI Interface
ADSP-21065L in Master Serial Interface
As shown in Figure 19, the AD7650 can be interfaced to the
ADSP-21065L using the serial interface in master mode without
any glue logic required. This mode combines the advantages of
reducing the number of wire connections and being able to read
the data during or after conversion at user convenience.
The AD7650 is configured for the internal clock mode (EXT/
INT
low) and acts, therefore, as the master device. The convert com-
mand can be generated by either an external low jitter oscillator
or, as shown, by a FLAG output of the ADSP-21065L or by a
frame output TFS of one serial port of the ADSP-21065L which
can be used as a timer. The serial port on the ADSP-21065L is
configured for external clock (IRFS = 0), rising edge active
(CKRE = 1), external late framed sync signals (IRFS = 0, LAFS = 1,
RFSR = 1) and active high (LRFS = 0). The serial port of the
ADSP-21065L is configured by writing to its receive control
register (SRCTL)—see ADSP-2106x SHARC User’s Manual.
Because the serial port within the ADSP-21065L will be seeing
a discontinuous clock, an initial word reading has to be done
after the ADSP-21065L has been reset to ensure that the serial
port is properly synchronized to this clock during each following
data read operation.
RFS
ADSP-21065L*
SHARC
CNVST
AD7650*
CS
SYNC
RD
DR
RCLK
FLAG OR TFS
SDOUT
SCLK
INVSYNC
INVSCLK
EXT/
INT
RDC/SDIN
SER/
PAR
DVDD
*ADDITIONAL PINS OMITTED FOR CLARITY
OVDD
OR
OGND
Figure 19. Interfacing to the ADSP-21065L Using the
Serial Master Mode
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