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參數(shù)資料
| 型號： | EVAL-AD7352EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL AD7352 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 3M |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±VREF/2 |
| 在以下條件下的電源（標準）： | 26mW @ 3MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7352 |
| 已供物品： | 板，CD |
AD7352
Rev. A | Page 17 of 20
POWER-UP TIMES
The AD7352 has two power-down modes: partial power-down
and full power-down, which are described in detail in the
Down Mode sections. This section deals with the power-up
time required when coming out of any of these modes. Note
that the recommended decoupling capacitors must be in place
on the REFA and REFB pins for the power-up times to apply.
To power up from partial power-down mode, one dummy cycle
is required. The device is fully powered up after approximately
333 ns have elapsed from the falling edge of CS. When the partial
power-up time has elapsed, the ADC is fully powered up, and
the input signal is acquired properly. The quiet time, tQUIET,
must still be allowed from the point where the bus goes back
into three-state after the dummy conversion to the next falling
edge of CS.
To power up from full power-down mode, approximately
6 ms should be allowed from the falling edge of CS, shown
in
as tPOWER-UP2.
Note that during power-up from partial power-down mode, the
track-and-hold, which is in hold mode while the part is powered
down, returns to track mode after the first SCLK edge that the
part receives after the falling edge of CS.
When power supplies are first applied to the AD7352, the ADC
can power up in either of the power-down modes or in normal
mode. Because of this, it is best to allow a dummy cycle to elapse
to ensure that the part is fully powered up before attempting a
valid conversion. Likewise, if the part is to be kept in partial
power-down mode immediately after the supplies are applied,
then two dummy cycles must be initiated. The first dummy
cycle must hold CS low until after the 10th SCLK falling edge; in
the second cycle, CS must be brought high between the second
and 10th SCLK falling edges (see
).
Alternatively, if the part is to be placed into full power-down
mode when the supplies are applied, three dummy cycles must
be initiated. The first dummy cycle must hold CS low until after
the 10th SCLK falling edge; the second and third dummy cycles
place the part into full power-down mode (see
and
the
section).
POWER vs. THROUGHPUT RATE
The power consumption of the AD7352 varies with the
throughput rate. When using very slow throughput rates and
as fast an SCLK frequency as possible, the various power-down
options can be used to make significant power savings. However,
the AD7352 quiescent current is low enough that, even without
using the power-down options, there is a noticeable variation in
power consumption with sampling rate. This is true whether a
fixed SCLK value is used or it is scaled with the sampling
rate. Figure 29 shows a plot of power vs. throughput rate when
operating in normal mode for a fixed maximum SCLK frequency
and a SCLK frequency that scales with the sampling rate. The
internal reference was used for Figure 29.
10
12
14
16
18
20
22
24
26
28
30
0
1000
2000
3000
PO
W
E
R
(
m
W
)
THROUGHPUT (kSPS)
070
44
-029
80MHz SCLK
VARIABLE SCLK
Figure 29. Power vs. Throughput Rate
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