參數(shù)資料
型號: EVAL-AD7265EDZ
廠商: Analog Devices Inc
文件頁數(shù): 5/29頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD7265 A/D CONV
標準包裝: 1
ADC 的數(shù)量: 2
位數(shù): 12
采樣率(每秒): 1M
數(shù)據(jù)接口: SPI?、QSPI?、MICROWIRE? 和 DSP
輸入范圍: 0 ~ 5 V
在以下條件下的電源(標準): 7mW @ 3V,17mW @ 5V
工作溫度: -40°C ~ 125°C
已用 IC / 零件: AD7265
已供物品:
AD7265
Rev. A | Page 12 of 28
The AD7265 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves, while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second-order and third-order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification, where it is the ratio
of the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in dBs.
Thermal Hysteresis
Thermal hysteresis is defined as the absolute maximum change
of reference output voltage after the device is cycled through
temperature from either
T_HYS+ = +25°C to TMAX to +25°C
or
T_HYS = +25°C to TMIN to +25°C
It is expressed in ppm by
6
10
)
C
25
(
)
_
(
)
C
25
(
)
(
×
°
°
=
REF
HYS
V
HYS
T
V
ppm
V
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the common-mode voltage of V
where:
V
and V
IN+
IN
of
frequency f
REF
(25°C) is VREF at 25°C.
V
S
as
REF
(T_HYS) is the maximum change of VREF at T_HYS+ or
T_HYS.
CMRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency f in the ADC output.
f
P S is the power at frequency fS in the ADC output.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but
not the converter’s linearity. PSRR is the maximum change in
the full-scale transition point due to a change in power supply
voltage from the nominal value (see Figure 4).
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