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參數(shù)資料
| 型號(hào)： | EVAL-AD7194EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 40/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR AD7194 |
| 設(shè)計(jì)資源： | EVAL-AD7zzzEBZ Schematic AD7194 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7194 |
| 已供物品： | 板，線纜 |
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AD7194
Data Sheet
Rev. A | Page 44 of 56
When a channel change occurs, the modulator and filter reset.
The complete settling time is required to generate the first
conversion after the channel change. Subsequent conversions
on this channel occur at 1/fADC.
CHANNEL
CONVERSIONS
CHANNEL A
CH A
CH B
CHANNEL B
1/
fADC
CH B
08566-
043
Figure 44. Channel Change (Sinc4 Chop Enabled)
When conversions are performed on a single channel and a
step change occurs, the ADC does not detect the change in
analog input; therefore, it continues to output conversions at
the programmed output data rate. However, it is at least two
conversions later before the output data accurately reflects the
analog input. If the step change occurs while the ADC is
processing a conversion, the ADC takes three conversions after
the step change to generate a fully settled result.
1/
fADC
ANALOG
INPUT
ADC
OUTPUT
FULLY
SETTLED
08566-
044
Figure 45. Asynchronous Step Change in Analog Input (Sinc4 Chop Enabled)
The cutoff frequency f3dB is equal to
f3dB = 0.24 × fADC
50 Hz/60 Hz Rejection (Sinc4 Chop Enabled)
When FS[9:0] is set to 96 and chopping is enabled, the output
data rate is equal to 12.5 Hz for a 4.92 MHz master clock. The
filter response shown in Figure 46 is obtained. The chopping
introduces notches at odd integer multiples of fADC/2. The
notches due to the sinc filter in addition to the notches intro-
duced by the chopping mean that simultaneous 50 Hz and
60 Hz rejection is achieved for an output data rate of 12.5 Hz.
The rejection at 50 Hz/60 Hz ± 1 Hz is typically 63 dB,
assuming a stable master clock.
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
25
50
75
100
125
150
FREQUENCY (Hz)
FI
L
T
E
R
G
AI
N
(
d
B)
08566-
045
Figure 46. Sinc4 Filter Response (FS[9:0] = 96, Chop Enabled)
The 50 Hz/60 Hz rejection can be improved by setting the
REJ60 bit in the mode register to 1. With FS[9:0] set to 96
and REJ60 set to 1, the filter response shown in Figure 47
is achieved. The output data rate is unchanged but the 50 Hz/
60 Hz (± 1 Hz) rejection is increased to 83 dB typically.
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
25
50
75
100
125
150
FREQUENCY (Hz)
FI
L
T
E
R
G
AI
N
(
d
B)
08566-
046
Figure 47. Sinc4 Filter Response (FS[9:0] = 96, Chop Enabled, REJ60 = 1)
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