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參數(shù)資料
| 型號： | EVAL-AD5821EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD5821 |
| 產品培訓模塊： | DAC Architectures |
| 標準包裝： | 1 |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 400k |
| 數(shù)據接口： | I²C |
| 設置時間： | 250µs |
| DAC 型： | 電流 |
| 工作溫度： | -30°C ~ 80°C |
| 已供物品： | 板，纜線，CD |
| 已用 IC / 零件： | AD5821 |
| 相關產品： | AD5821BCBZ-REEL7DKR-ND - IC DAC 10BIT CURRENTSINK 9WLCSP AD5821BCBZ-REEL7CT-ND - IC DAC 10BIT CURRENTSINK 9WLCSP AD5821BCBZ-REEL7TR-ND - IC DAC 10BIT CURRENTSINK 9WLCSP AD5821BCBZ-REEL-ND - IC DAC 10BIT CURRENTSINK 9WLCSP |
AD5821
Rev. 0 | Page 3 of 16
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance RL = 25 Ω connected to VDD; all specifications TMIN to TMAX,
unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DC PERFORMANCE
VDD = 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V
with reduced performance
Resolution
10
Bits
117 μA/LSB
±1.5
±4
LSB
±1
LSB
Guaranteed monotonic over all codes
0
1
5
mA
All 0s loaded to DAC
Offset Error @ Code 162
0.5
mA
Gain Error2
±0.6
% of FSR
@ 25°C
10
μA/°C
Gain Error Drift2, 5
±0.2
±0.5
LSB/°C
OUTPUT CHARACTERISTICS
Minimum Sink Current4
3
mA
Maximum Sink Current
120
mA
Output Current During XSHUTDOWN
80
nA
XSHUTDOWN = 0
Output Compliance5
0.6
VDD
V
Output voltage range over which maximum 120 mA
sink current is available
Output Compliance5
0.48
VDD
V
Output voltage range over which 90 mA sink current
is available
Power-Up Time
20
μs
To 10% of FS, coming out of power-down mode; VDD = 5 V
LOGIC INPUTS (XSHUTDOWN)5
Input Current
±1
μA
Input Low Voltage, VINL
0.54
V
VDD = 2.7 V to 5.5 V
Input High Voltage, VINH
1.3
V
VDD = 2.7 V to 5.5 V
Pin Capacitance
3
pF
LOGIC INPUTS (SCL, SDA)5
Input Low Voltage, VINL
0.3
+0.54
V
VDD = 2.7 V to 3.6 V
Input High Voltage, VINH
1.26
VDD + 0.3
V
VDD = 2.7 V to 3.6 V
Input Low Voltage, VINL
0.3
+0.54
V
VDD = 3.6 V to 5.5 V
Input High Voltage, VINH
1.4
VDD + 0.3
V
VDD = 3.6 V to 5.5 V
Input Leakage Current, IIN
±1
μA
VIN = 0 V to VDD
Input Hysteresis, VHYST
0.05 VDD
V
Digital Input Capacitance, CIN
6
pF
50
ns
Pulse width of spike suppressed
POWER REQUIREMENTS
VDD
2.7
5.5
V
IDD (Normal Mode)
IDD specification is valid for all DAC codes
VDD = 2.7 V to 3.6 V
2.5
4
mA
VINH = 1.8 V, VINL = GND, VDD = 3.6 V
0.5
μA
VINH = 1.8 V, VINL = GND
1 Temperature range is as follows: B Version = 30°C to +85°C.
2 See the
section.
3 Linearity is tested using a reduced code range: Code 32 to Code 1023.
4 To achieve near zero output current, use the power-down feature.
5 Guaranteed by design and characterization; not production tested. XSHUTDOWN is active low. SDA and SCL pull-up resistors are tied to 1.8 V.
6 Input filtering on both the SCL and the SDA inputs suppresses noise spikes that are less than 50 ns.
7 XSHUTDOWN is active low.
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