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參數資料
| 型號： | EVAL-AD5791SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 13/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5791 |
| 標準包裝： | 1 |
| DAC 的數量： | 1 |
| 位數： | 20 |
| 數據接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 設置時間： | 1µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 125°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD5791 |
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Data Sheet
AD5791
Rev. D | Page 19 of 28
THEORY OF OPERATION
The AD5791 is a high accuracy, fast settling, single, 20-bit,
serial input, voltage output DAC. It operates from a VDD supply
voltage of 7.5 V to 16.5 V and a VSS supply of 16.5 V to 2.5 V.
Data is written to the AD5791 in a 24-bit word format via a 3-wire
serial interface. The AD5791 incorporates a power-on reset
circuit that ensures the DAC output powers up to 0 V with the
VOUT pin clamped to AGND through a ~6 kΩ internal resistor.
DAC ARCHITECTURE
The architecture of the AD5791 consists of two matched DAC
sections. A simplified circuit diagram is shown in Figure 49.
The six MSBs of the 20-bit data-word are decoded to drive 63
switches, E0 to E62. Each of these switches connects one of 63
matched resistors to either the VREFP or VREFN voltage. The
remaining 14 bits of the data-word drive the S0 to S13 switched
of a 14-bit voltage mode R-2R ladder network. To ensure
performance to specification, the reference inputs must be force
sensed with external amplifiers.
2R
S0
2R
S1
2R
S11
2R
E62
2R
E61
2R
E0
14-BIT R-2R LADDER
.....................
..........
RR
R
2R
VREFPF
VREFPS
VREFNF
VREFNS
VOUT
SIX MSBs DECODED INTO
63 EQUAL SEGMENTS
089
64-
050
Figure 49. DAC Ladder Structure
SERIAL INTERFACE
The AD5791 has a 3-wire serial interface (SYNC, SCLK, and
SDIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs (see Figure 2 for a
timing diagram).
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK, which can operate at up to 50 MHz. The
input register consists of a R/W bit, three address bits, and
twenty register bits as shown in Table 7. The timing diagram for
this operation is shown in Figure 2.
Table 7. Input Shift Register Format
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB0
R/W
Register address
Register data
Table 8. Decoding the Input Shift Register
R/W
Register Address
Description
0
No operation (NOP; used in readback operations
0
1
Write to the DAC register
0
1
0
Write to the control register
0
1
Write to the clearcode register
0
1
0
Write to the software control register
1
0
1
Read from the DAC register
1
0
1
0
Read from the control register
1
0
1
Read from the clearcode register
1 X is don’t care.
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