參數(shù)資料
型號(hào)： EVAL-AD5764EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/28頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5764
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 4
位數(shù)： 16
采樣率（每秒）： 30M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
設(shè)置時(shí)間： 8µs
DAC 型： 電壓
工作溫度： -40°C ~ 85°C
已供物品： 板，纜線，CD
已用 IC / 零件： AD5764
相關(guān)產(chǎn)品： AD5764CSUZ-REEL7-ND - IC DAC 16BIT QUAD BIPO 32-TQFP
AD5764BSUZ-REEL7-ND - IC DAC 16BIT QUAD VOUT 32-TQFP
AD5764ASUZ-REEL7-ND - IC DAC 16BIT QUAD VOUT 32-TQFP
AD5764BSUZ-ND - IC DAC 16BIT QUAD VOUT 32-TQFP
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AD5764
Data Sheet
Rev. F | Page 20 of 28
The output voltage expression for the AD5764 is given by
TRANSFER FUNCTION
×
+
×
=
536
,
65
4
2
D
V
REFIN
OUT
Table 7 and Table 8 show the ideal input code to output voltage
relationship for the AD5764 for both offset binary and twos
complement data coding, respectively.
where:
D is the decimal equivalent of the code loaded to the DAC.
VREFIN is the reference voltage applied at the REFAB/REFCD pins.
Table 7. Ideal Output Voltage to Input Code Relationship—
Offset Binary Data Coding
Digital Input
Analog Output
ASYNCHRONOUS CLEAR (CLR)
MSB
LSB
VOUTx
1111
+2 VREF × (32,767/32,768)
CLR is a negative edge triggered clear that allows the outputs to
be cleared to either 0 V (twos complement coding) or negative
full scale (offset binary coding). It is necessary to maintain CLR
low for a minimum amount of time (see
) for the operation
to complete. When the
CLR signal is returned high, the output
remains at the cleared value until a new value is programmed. If
at power-on, CLR is at 0 V, then all DAC outputs are updated
with the clear value. A clear can also be initiated through software
by writing Command 0x04XXXX to the AD5764.
1000
0000
0001
+2 VREF × (1/32,768)
1000
0000
0 V
0111
1111
2 VREF × (1/32,768)
0000
2 VREF × (32,767/32,768)
Table 8. Ideal Output Voltage to Input Code Relationship—
Twos Complement Data Coding
Digital Input
Analog Output
MSB
LSB
VOUTx
0111
1111
+2 VREF × (32,767/32,768)
0000
0001
+2 VREF × (1/32,768)
0000
0 V
1111
2 VREF × (1/32,768)
1000
0000
2 VREF × (32,767/32,768)
Table 9. Input Shift Register Bit Map
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15:DB0
R/W
0
REG2
REG1
REG0
A2
A1
A0
Data
Table 10. Input Shift Register Bit Functions
Bit
Description
R/W
Indicates a read from or a write to the addressed register.
REG2, REG1, REG0
Used in association with the address bits to determine if a read or write operation is to the data register, offset
register, coarse gain register, fine gain register, or function register.
REG2
REG1
REG0
Function
0
Function register
0
1
0
Data register
0
1
Coarse gain register
1
0
Fine gain register
1
0
1
Offset register
A2, A1, A0
These bits are used to decode the DAC channels.
A2
A1
A0
Channel Address
0
DAC A
0
1
DAC B
0
1
0
DAC C
0
1
DAC D
1
0
All DACs
Data
Data bits.
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