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參數(shù)資料
| 型號： | EVAL-AD5545SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5545 |
| 標準包裝： | 1 |
| 系列： | * |
AD5545/AD5555
Data Sheet
Rev. G | Page 6 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5545/
AD5555
TOP VIEW
(Not to Scale)
8
7
6
5
1
4
3
2
9
10
11
12
16
13
14
15
CS
DGND
CLK
VDD
MSB
LDAC
RS
SDI
VREFB
RFBB
AGNDB
IOUTB
RFBA
AGNDA
IOUTA
VREFA
02918- 0- 002
Figure 4. 16-Lead TSSOP
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
RFBA
Establish voltage output for DAC A by connecting this pin to an external amplifier output.
2
VREFA
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. This pin can
be tied to the VDD pin.
3
IOUTA
DAC A Current Output.
4
AGNDA
DAC A Analog Ground.
5
AGNDB
DAC B Analog Ground.
6
IOUTB
DAC B Current Output.
7
VREFB
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage.
This pin can be tied to the VDD pin.
8
RFBB
Establish voltage output for DAC B by the RFBB pin connecting to an external amplifier output.
9
SDI
Serial Data Input. Input data loads directly into the shift register.
10
RS
Reset Pin, Active Low Input. Input registers and DAC registers are set to all 0s or midscale. Register
Data = 0x0000 when MSB = 0. Register Data = 0x8000 for AD5545 and 0x2000 for AD5555 when
MSB = 1.
11
CS
Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register
data to the input register when CS/LDAC returns high. This does not affect LDAC operation.
12
DGND
Digital Ground Pin.
13
VDD
Positive Power Supply Input. Specified range of operation 5 V ± 10%.
14
MSB
MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system power-on.
Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can also be tied
permanently to ground or VDD.
15
LDAC
Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC
registers. Asynchronous active low input. See Table 7 and Table 8 for operation.
16
CLK
Clock Input. Positive edge clocks data into shift register.
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