參數(shù)資料
型號： EVAL-AD5541ASDZ
廠商： Analog Devices Inc
文件頁數(shù)： 19/20頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5541
標(biāo)準(zhǔn)包裝： 1
系列： nanoDAC™
DAC 的數(shù)量： 1
位數(shù)： 16
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
設(shè)置時間： 1µs
DAC 型： 電壓
已供物品： 板
已用 IC / 零件： AD5541
AD5541A
Rev. A | Page 8 of 20
08
51
6-
0
04
NOTES
1. FOR INCREASED RELIABILITY OF THE SOLDER
JOINTS AND MAXIMUM THERMAL CAPABILITY,
IT IS RECOMMENDED THAT THE PAD BE SOLDERED
TO THE SUBSTRATE, GND.
3
SCLK
4
DIN
1
REF
2
CS
6VOUT
5CLR
8GND
7VDD
TOP VIEW
(Not to Scale)
AD5541A-1
Figure 5. AD5541A-1 8-Lead LFCSP Pin Configuration
08
51
6-
0
05
1
VDD
2
VOUT
3
AGND
4
REF
5
10 VLOGIC
9DGND
8
7DIN
6SCLK
TOP VIEW
(Not to Scale)
AD5541A
CS
LDAC
NOTES
1. FOR INCREASED RELIABILITY OF THE SOLDER
JOINTS AND MAXIMUM THERMAL CAPABILITY,
IT IS RECOMMENDED THAT THE PAD BE SOLDERED
TO THE SUBSTRATE, GND.
Figure 6. AD5541A 10-Lead LFCSP Pin Configuration
Table 7. AD5541A-1 and AD5541A Pin Function Descriptions
Pin No.
8-Lead LFCSP
10-Lead LFCSP
Mnemonic
Description
1
4
REF
Voltage Reference Input for the DAC. Connect to an external 2.5 V reference. The
reference can range from 2 V to VDD.
2
5
CS
Logic Input Signal. The chip select signal is used to frame the serial data input.
3
6
SCLK
Clock Input. Data is clocked into the serial input register on the rising edge of SCLK.
Duty cycle must be between 40% and 60%.
4
7
DIN
Serial Data Input. This device accepts 16-bit words. Data is clocked into the serial input
register on the rising edge of SCLK.
5
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all
LDAC pulses are ignored. When CLR is activated, the serial input register and the DAC
register are cleared to zero scale.
6
2
VOUT
Analog Output Voltage from the DAC.
9
DGND
Digital Ground. Ground reference for digital circuitry.
7
1
VDD
Analog Supply Voltage.
8
GND
Ground Reference Point for Both Analog and Digital Circuitry.
3
AGND
Ground Reference Point for Analog Circuitry.
10
VLOGIC
Logic Power Supply.
8
LDAC
LDAC Input. When this input is taken low, the DAC register is simultaneously updated
with the contents of the serial input register.
EPAD
Exposed Pad. For increased reliability of the solder joints and maximum thermal
capability, it is recommended that the pad be soldered to the substrate, GND.
1 N/A means not applicable.
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EVAL-AD5542ASDZ 功能描述:BOARD EVAL FOR AD5542 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:nanoDAC™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5543SDZ 功能描述:BOARD EVAL FOR AD5543 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5544SDZ 功能描述:BOARD EVAL FOR AD5544 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5545SDZ 功能描述:BOARD EVAL FOR AD5545 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5546SDZ 功能描述:BOARD EVAL FOR AD5546 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
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