- 您現在的位置：買賣IC網 > PDF目錄17070 > EVAL-AD5443EBZ (Analog Devices Inc)BOARD EVAL FOR AD5433 PDF資料下載
參數資料
| 型號： | EVAL-AD5443EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 24/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5433 |
| 標準包裝： | 1 |
| DAC 的數量： | 1 |
| 位數： | 12 |
| 采樣率（每秒）： | 50M |
| 數據接口： | SPI?、QSPI?、MICROWIRE? 和 DSP |
| 設置時間： | 50ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 125°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD5443 |
Data Sheet
AD5426/AD5432/AD5443
Rev. G | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IOUT1 1
IOUT2 2
GND
3
SCLK
4
SDIN
5
RFB
10
VREF
9
VDD
8
SDO
7
SYNC
6
AD5426/
AD5432/
AD5443
TOP VIEW
(Not to Scale)
03162-005
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
IOUT1
DAC Current Output.
2
IOUT2
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
3
GND
Digital Ground Pin.
4
SCLK
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
input. Alternatively, by means of the serial control bits, the device may be configured such that data is clocked into
the shift register on the rising edge of SCLK. The device can accommodate clock rates up to 50 MHz.
5
SDIN
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By
default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the
user to change the active edge to rising edge.
6
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the mode, the serial
interface counts clocks, and data is latched to the shift register on the 16th active clock edge.
7
SDO
Serial Data Output. This allows a number of parts to be daisy-chained. By default, data is clocked into the shift
register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the
alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes
the DAC register contents available for readback on the SDO pin, clocked out on the opposite edges to the active
clock edge. SDO operates with a VDD of 3.0 V to 5.5 V.
8
VDD
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
9
VREF
DAC Reference Voltage Input.
10
RFB
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output.
相關PDF資料 |
PDF描述 |
|---|---|
| DC1011A-A | BOARD DELTA SIGMA ADC LTC2498 |
| NR5040T100M | INDUCTOR 10UH 2.1A 20% SMD |
| EVAL-AD5405EBZ | BOARD EVAL FOR AD5405 |
| EVAL-AD5062EBZ | BOARD EVAL FOR AD5062 |
| V48C2E50BL2 | CONVERTER MOD DC/DC 2V 50W |
相關代理商/技術參數 |
參數描述 |
|---|---|
| EVAL-AD5443SDZ | 功能描述:BOARD EVAL FOR AD5443 RoHS:是 類別:編程器，開發(fā)系統 >> 評估板 - 數模轉換器 (DAC) 系列:* 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數量:4 位數:12 采樣率（每秒）:- 數據接口:串行，SPI? 設置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-AD5444EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-AD5444EBZ | 制造商:Analog Devices 功能描述:EVAL KIT FOR 12-/14BIT HIGH BANDWIDTH MULTIPLYING DACS W/ SE - Bulk |
| EVAL-AD5445EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD - Bulk |
| EVAL-AD5445EBZ | 功能描述:BOARD EVALUATION FOR AD5445 RoHS:是 類別:編程器，開發(fā)系統 >> 評估板 - 數模轉換器 (DAC) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數量:4 位數:12 采樣率（每秒）:- 數據接口:串行，SPI? 設置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
發(fā)布緊急采購，3分鐘左右您將得到回復。