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參數資料
| 型號： | EVAL-AD5242EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 6/20頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD5242 |
| 標準包裝： | 1 |
| 主要目的： | 數字電位器 |
| 已用 IC / 零件： | AD5242 |
| 已供物品： | 板 |
| 相關產品： | AD5242BRUZ100-RL7DKR-ND - IC POT DGTL 100K 256POS 16TSSOP AD5242BRUZ1M-REEL7-ND - IC POT DGTL 1M 256POS 16-TSSOP AD5242BRUZ100-RL7CT-ND - IC POT DGTL 100K 256POS 16TSSOP AD5242BRUZ1M-ND - IC POT DGTL DUAL 256POS 16-TSSOP AD5242BRZ100-ND - IC POT DGTL DUAL 256POS 16SOIC AD5242BRZ100-REEL7-ND - IC POT DGTL DUAL 256POS 16SOIC AD5242BRZ1M-ND - IC POT DGTL DUAL 256POS 16SOIC AD5242BRZ10-REEL7-ND - IC POT DGTL DUAL 256POS 16SOIC AD5242BRZ10-ND - IC POT DGTL DUAL 256POS 16SOIC AD5242BRU100RLDKR-ND - IC DGTL POT 256POS 16-TSSOP 更多... |
AD5241/AD5242
Rev. C | Page 14 of 20
4.
Unlike the write mode, the data byte follows immediately
after the acknowledgment of the slave address byte in
Frame 2 read mode. Data is transmitted over the serial bus
in sequences of nine clock pulses (slightly different from
the write mode, there are eight data bits followed by a no
acknowledge Logic 1 bit in read mode). Similarly, the
transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL (see Figure 5).
MULTIPLE DEVICES ON ONE BUS
Figure 33 shows four AD5242 devices on the same serial bus.
Each has a different slave address because the state of their AD0
and AD1 pins are different. This allows each RDAC within each
device to be written to or read from independently. The master
device output bus line drivers are open-drain pull-downs in a
fully I2C-compatible interface. Note, a device is addressed properly
only if the bit information of AD0 and AD1 in the slave address
byte matches with the logic inputs at the AD0 and AD1 pins of
that particular device.
5.
When all data bits have been read or written, a stop condition
is established by the master. A stop condition is defined as
a low-to-high transition on the SDA line while SCL is high.
In write mode, the master pulls the SDA line high during
the tenth clock pulse to establish a stop condition (see
Figure 4). In read mode, the master issues a no acknowledge
for the ninth clock pulse (that is, the SDA line remains high).
The master then brings the SDA line low before the tenth
clock pulse, which goes high to establish a stop condition
(see Figure 5).
LEVEL-SHIFT FOR BIDIRECTIONAL INTERFACE
While most old systems can operate at one voltage, a new
component may be optimized at another. When they operate
the same signal at two different voltages, a proper method of
level-shifting is needed. For instance, a 3.3 V E2PROM can be
used to interface with a 5 V digital potentiometer. A level-shift
scheme is needed to enable a bidirectional communication so that
the setting of the digital potentiometer can be stored to and
M1 and M2 can be N-channel FETs (2N7002) or low threshold
FDV301N if VDD falls below 2.5 V.
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. During the write cycle, each data byte updates
the RDAC output. For example, after the RDAC has acknowledged
its slave address and instruction bytes, the RDAC output is
updated. If another byte is written to the RDAC while it is still
addressed to a specific slave device with the same instruction,
this byte updates the output of the selected slave device. If
different instructions are needed, the write mode has to start a
completely new sequence with a new slave address, instruction,
and data bytes transferred again. Similarly, a repeated read
function of the RDAC is also allowed.
RP
SD
G
M1
G
M2
3.3V
E2PROM
RP
5V
AD5242
SCL2
SDA2
VDD = 5V
VDD = 3.3V
SCL1
SDA1
0
09
26
-02
4
Figure 32. Level-Shift for Different Voltage Devices Operation
READBACK RDAC VALUE
Specific to the AD5242 dual-channel device, the channel of
interest is the one that was previously selected in the write mode.
In addition, to read both RDAC values consecutively, users have to
perform two write-read cycles. For example, users may first specify
the RDAC1 subaddress in write mode (it is not necessary to issue
the data byte and stop condition), and then change to read mode
to read the RDAC1 value. To continue reading the RDAC2 value,
users have to switch back to write mode, specify the subaddress,
and then switch once again to read mode to read the RDAC2
value. It is not necessary to issue the write mode data byte or
the first stop condition for this operation. Users should refer to
SDA SCL
AD5242
AD1
AD0
SDA
SCL
RP
SDA SCL
AD5242
VDD
AD1
AD0
SDA SCL
AD1
AD0
AD5242
VDD
SDA SCL
AD5242
VDD
AD1
AD0
MASTER
5V
0
09
26
-02
3
Figure 33. Multiple AD5242 Devices on One Bus
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