參數(shù)資料
型號: EVAL-AD1936EB
廠商: Analog Devices, Inc.
元件分類: Codec
英文描述: 4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
中文描述: 4模數(shù)轉換器/ 8鎖相環(huán),192千赫,24位編解碼器數(shù)模轉換器
文件頁數(shù): 14/30頁
文件大?。?/td> 376K
代理商: EVAL-AD1936EB
AD1935/AD1936/AD1937/AD1938/AD1939
Preliminary Technical Data
Rev. Pr
I
| Page 14 of 30
LRCLK
BCLK
DATA
LEFT 1
RIGHT 1
SLOT 5
RIGHT 2
SLOT 6
32 BCLKs
MSB
MSB–1
MSB–2
256 BCLKs
LEFT 2
SLOT 4
SLOT 7
SLOT 8
LRCLK
BCLK
DATA
SLOT 1
SLOT 2
SLOT 3
Figure 16. ADC TDM (8-channel I
2
Smode )
LRCLK
BCLK
DATA
LEFT 1
RIGHT 1
LEFT 3
RIGHT 2
RIGHT 3
32 BCLKs
MSB
MSB–1
MSB–2
256 BCLKs
LEFT 2
SLOT 4
LEFT 4
RIGHT 4
LRCLK
BCLK
DATA
SLOT 1
SLOT 2
SLOT 5
SLOT 6
SLOT 3
SLOT 7
SLOT 8
Figure 17. DAC TDM (8-channel I
2
S mode)
FSTDM
ADC L1
ADC R1
ADC L2
ADC R2
AUX ADC L1
AUX ADC R1
AUX ADC L2
AUX ADC R2
DAC L1
DAC R1
DAC L2
DAC L3
DAC R3
DAC L4
MSB TDM
CH
LEFT
RIGHT
I
2
S - MSB RIGHT
I
2
S - MSB LEFT
BCLK
TDM
ASDATA1
TDM (OUT)
ASDATA
DSDATA1
TDM (IN)
DSDATA1
AUX LRCLK
(FROM AUX ADC 1)
AUX BCLK
(FROM AUX ADC 1)
AUX DATA IN 1
(FROM AUX ADC 1)
AUX DATA IN 2
(FROM AUX ADC 2)
AUX BCLK FREQUENCY IS 64
×
FRAME-RATE; TDM BCLK FREQUENCY IS 256
×
FRAME-RATE.
T
A
2
S
MSB TDM
CH
32
32
MSB TDM
CH
MSB TDM
CH
I
2
S - MSB RIGHT
I
2
S - MSB LEFT
DAC R2
DAC R4
Figure 18. AUX 256 Mode Timing (Note that the Clocks Are Not to Scale)
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