參數(shù)資料
型號(hào)： EVAL-AD1870EB
廠(chǎng)商： Analog Devices, Inc.
英文描述： Single-Supply 16-Bit Stereo ADC
中文描述： 單電源16位立體聲ADC
文件頁(yè)數(shù)： 1/20頁(yè)
文件大?。?/td> 283K
代理商： EVAL-AD1870EB
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
L
R
CK
WCLK
BCLK
DGND1
DV
DD
1
RDEDGE
S/
M
384/
256
AV
DD
V
IN
L
CAPL1
CAPL2
AGNDL
V
REF
L
CLKIN
TAG
SOUT
DV
DD
2
RESET
MSBDLY
R
L
JUST
AGND
V
IN
R
CAPR1
CAPR2
AGNDR
V
REF
R
SERIAL OUTPUT
INTERFACE
THREE-STAGE FIR
DECIMATION
FILTER
DGND2
THREE-STAGE FIR
DECIMATION
FILTER
CLOCK
DIVIDER
VOLTAGE
REFERENCE
DAC
SINGLE-TO-
DIFFERENTIAL INPUT
CONVERTER
SINGLE-TO-
DIFFERENTIAL INPUT
CONVERTER
AD1870
DAC
DAC
DAC
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
Single-Supply
16-Bit - Stereo ADC
FEATURES
Single 5 V Power Supply
Single-Ended Dual-Channel Analog Inputs
92 dB (Typ) Dynamic Range
90 dB (Typ) S/(THD + N)
0.006 dB Decimator Pass-Band Ripple
Fourth Order, 64 Oversampling - Modulator
Three-Stage, Linear-Phase Decimator
256 f
S
or 384 f
S
Input Clock
Less than 100 W (Typ) Power-Down Mode
Input Overrange Indication
On-Chip Voltage Reference
Flexible Serial Output Interface
28-Lead SOIC Package
APPLICATIONS
Consumer Digital Audio Receivers
Digital Audio Recorders, Including Portables
CD-R, DCC, MD, and DAT
Multimedia and Consumer Electronics Equipment
Sampling Music Synthesizers
AD1870
*
shapes the one-bit comparator’s quantization noise out of the
audio pass band. The high order of the modulator randomizes the
modulator output, reducing idle tones in the AD1870 to very
low levels. Because its modulator is single bit, the AD1870 is
inherently monotonic and has no mechanism for producing
differential linearity errors.
The input section of the AD1870 uses autocalibration to correct
any dc offset voltage present in the circuit, provided that the inputs
are ac-coupled. The single-ended dc input voltage can swing
between 0.7 V and 3.8 V typically. The AD1870 antialias input
circuit requires four external 470 pF NPO ceramic chip filter
capacitors, two for each channel. No active electronics are needed.
Decoupling capacitors for the supply and reference pins are
also required.
The dual-digital decimation filters are triple-stage, finite impulse
response filters for effectively removing the modulator’s high
frequency quantization noise and reducing the 64
×
f
S
single-bit
output data rate to an f
S
word rate. They provide linear phase
and a narrow transition band that properly digitizes 20 kHz signals
at a 44.1 kHz sampling frequency. Pass-band ripple is less than
0.006 dB, and stop-band attenuation exceeds 90 dB.
(
Continued on Page 7)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
Analog Devices, Inc., 2002
PRODUCT OVERVIEW
The AD1870 is a stereo, 16-bit oversampling ADC based on
sigma-delta ( - ) technology intended primarily for digital
audio bandwidth applications requiring a single 5 V power supply.
Each single-ended channel consists of a fourth order one-bit
noise shaping modulator and a digital decimation filter. An on-chip
voltage reference, stable over temperature and time, defines the
full-scale range for both channels. Digital output data from both
channels are time multiplexed to a single, flexible serial inter-
face. The AD1870 accepts a 256
×
f
S
or a 384
×
f
S
input clock
(f
S
is the sampling frequency) and operates in both serial port
Master and Slave Modes. In Slave Mode, all clocks must be ex-
ternally derived from a common source.
Input signals are sampled at 64
×
f
S
onto internally buffered
switched capacitors, eliminating external sample-and-hold ampli-
fiers and minimizing the requirements for antialias filtering at the
input. With simplified antialiasing, linear phase can be preserved
across the pass band. The on-chip single-ended-to-differential sig-
nal converters save the board designer from having to provide
them externally. The AD1870’s internal differential architecture
provides increased dynamic range and excellent power supply
rejection characteristics. The AD1870’s proprietary fourth order
differential switched-capacitor - modulator architecture
*
Protected by U.S. Patent Numbers 5055843, 5126653; others pending.
相關(guān)PDF資料
PDF描述
EVAL-AD1896EB Automotive Low-Cost Non-Volatile FPGA Family; Voltage: 1.2V; Grade: -5; Package: Lead-Free ftBGA; Pins: 256; Temperature: AUTO; LUTs (k): 8
EVAL-AD1928EBZ 2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
EVAL-AD1928EB 2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
EVAL-AD1938EB 4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
EVAL-AD1939EB 4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-AD1871EB 制造商:Analog Devices 功能描述:STEREO AUD, 24BIT, 96 KHZ, MULTIBIT- ADC - Bulk
EVAL-AD1871EBZ 功能描述:BOARD EVAL FOR AD1871 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:* 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件
EVAL-AD1895EB 制造商:Analog Devices 功能描述:EVAL BD FOR AD1895 192KHZ 8:1 STEREO - Bulk
EVAL-AD1896EB 制造商:Analog Devices 功能描述:Evaluation Kit For 24-Bit, High-Performance, Single-Chip, Second Generation Asynchronous Sample Rate Converter 制造商:Analog Devices 功能描述:EVAL KIT FOR AD1896 7.75:1 TO 1:8, 192KHZ STEREO ASRC EVAL B - Bulk
EVAL-AD1928EB 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*