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參數(shù)資料
| 型號： | ES6028F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Vibratto DVD Processor |
| 中文描述： | Vibratto DVD處理器 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 93K |
| 代理商： | ES6028F |
ESS Technology, Inc.
SAM0462-031704
3
ES6028 PRODUCT BRIEF
ES6028 PIN DESCRIPTION
ES6028 PIN DESCRIPTION
Table 1 lists the pin descriptions for the ES6028.
Table 1 ES6028 Pin Description
Name
Pin Numbers
I/O
Definition
VEE
1,18, 27, 59, 68, 75,
92, 99, 104, 130,
148, 157, 159, 164,
183, 193, 201
P
I/O power supply.
LA[21:0]
2-7, 10-16, 19-23,
204-207
O
RISC port address bus.
VSS
8, 17, 26, 34, 43,
60, 67, 76, 84, 91,
98, 103, 120, 129,
138, 147, 156, 163,
171, 177, 184, 192,
200, 208
G
Ground.
VCC
9, 35, 44, 83, 121,
139, 172
P
Core power supply.
RESET#
24
I
Reset input, active-low.
TDMDX
25
O
TDM transmit data output.
RSEL
I
LCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-k
resistor; read only during reset.
TDMDR
28
I
TDM receive data input.
TDMCLK
29
I
TDM clock input.
TDMFS
30
I
TDM frame sync input.
TDMTSC#
31
O
TDM output enable.
TWS
32
O
Audio transmit frame sync output.
SEL_PLL2
I
System and DSCK output clock frequency selection is made at the rising edge of
RESET#. The matrix below lists the available clock frequencies and their
respective PLL bit settings. Strapped to VCC or ground via 4.7-k
resistor; read
only during reset.
RSEL
Selection
0
16-bit ROM
1
8-bit ROM
SEL_PLL2
0
0
0
0
1
1
1
1
SEL_PLL1
0
0
1
1
0
0
1
1
SEL_PLL0 Clock Type
0
1
0
1
0
1
0
1
DCLK x 4.25
Reserved
Bypass mode
DCLK x 3.75
DCLK x 4.5
Reserved
DCLK x 3.5
DCLK x 4
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相關(guān)代理商/技術(shù)參數(shù) |
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| ES60BV004 | 制造商:Easy Braid Co 功能描述:CONICAL SHARP 0.4MM |
| ES60BV011 | 制造商:Easy Braid Co 功能描述:BEVEL 1.10MM |
| ES60CH010 | 制造商:Easy Braid Co 功能描述:CHISEL 30DEG 1.0MM |
| ES60CH015 | 制造商:Easy Braid Co 功能描述:CHISEL 30DEG 1.50MM |
| ES60CH018 | 制造商:Easy Braid Co 功能描述:CHISEL 30DEG 1.80MM |
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