參數(shù)資料
型號(hào): ES4227
廠商: Electronic Theatre Controls, Inc.
英文描述: Internet Set-Top Box Solution
中文描述: 互聯(lián)網(wǎng)機(jī)頂盒解決方案
文件頁數(shù): 3/8頁
文件大?。?/td> 94K
代理商: ES4227
ESS Technology, Inc.
SAM0378-053001
3
ES4228/ES4227 PRODUCT BRIEF
ES4228 PIN DESCRIPTION
Table 1 lists the pin descriptions for the ES4228.
Table 1 ES4228 Pin Descriptions List
Name
1, 9, 18, 27, 35, 44, 51, 59,
68, 75, 83, 92, 99, 104, 111,
121, 130, 139, 148, 157,
164, 172, 183, 193, 201
LA[21:0]
23:19, 16:10, 7:2, 207:204
8, 17, 26, 34, 43, 52, 60,
67, 76, 84, 91, 98, 103, 112,
120, 129, 138, 147, 156,
163, 171, 177, 184, 192,
Number
I/O
I
Description
VCC
3.45 V power supply.
O
I
Device address output.
VSS
200, 208
24
Ground.
RESET#
TDMDX
I
Reset input, active low.
TDM transmit data.
ROM Select.
RSEL
0
1
25
O
I
RSEL
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS
SEL_PLL1
TSD
28
29
30
31
32
I
I
I
TDM receive data.
TDM clock input.
TDM frame sync.
TDM output enable, active low.
Audio transmit frame sync.
Refer to the description and matrix for SEL_PLL0 pin 33.
Audio transmit serial data port.
System and DSCK output clock frequency selection at reset time. The matrix
below lists the available clock frequencies and their respecitve PLL bit
settings.
SEL_PLL2
SEL_PLL1
SEL_PLL0 Clock Output
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
O
O
I
O
I
33
SEL_PLL0
SEL_PLL2
MCLK
TBCK
RSD
RWS
RBCK
APLLCAP
XIN
XOUT
36
39
40
45
46
47
48
49
50
I
Refer to the description and matrix for SEL_PLL0 pin 33.
Audio master clock for audio DAC.
Audio transmit bit clock.
Audio receive serial data.
Audio receive frame sync.
Audio receive bit clock.
Analog PLL Capacitor.
Crystal input.
Crystal output.
I/O
I/O
I
I
I
I
I
O
Selection
8-bit ROM
16-bit ROM
0
1
0
1
0
1
0
1
VCO doesn’t work.
27 MHz
Bypass mode
54 MHz
121.5 MHz
81 MHz
94.5 MHz
108 MHz
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