
ESS Technology, Inc.
SAM0429-112001
3
ES3889 PRODUCT BRIEF
PIN DESCRIPTION
AUX1
9
I/O
Servo reverse or control.
DSC_S
10
I
Strobe for programming to access internal registers.
AUX2
11
I/O
Servo LDON or control.
DCLK
12
O
Dual-purpose pin DCLK is the MPEG decoder clock.
EXT_CLK
I
EXT_CLK is the external clock. EXT_CLK is an input during bypass PLL mode.
RESET_B
13
I
Video reset, active-low.
AUX7
14
I/O
Servo BRKM/sense
VFD_DI
I
Vacuum fluorescent display data in.
MUTE
15
O
Audio mute.
MCLK
17
I
Audio master clock.
AUX8
18
I/O
Servo mute/open
VFD_CLK
I
Vacuum fluorescent display clock.
TWS
19
I
Dual-purpose pin TWS is the transmit audio frame sync.
SPLL_OUT
O
SPLL_OUT is the select PLL output.
AUX9
20
I/O
General-purpose input/output.
SQS0
I
Servo SQS0 or control.
TSD
21
I
Transmit audio data input.
TBCK
22
I
Transmit audio bit clock.
RWS
23
O
Dual-purpose pin RWS is the receive audio frame sync.
SEL_PLL1
I
SEL_PLL[1:0] select the PLL clock frequency for the DCLK output.
RSTOUT_B
24
O
Reset output, active-low.
RSD
33
O
Dual-purpose. RSD is the receive audio data input.
SEL_PLL0
I
SEL_PLL0 along with SEL_PLL1 select the PLL clock frequency for the DCLK
output. Refer to pin number 23.
AUX10
34
I/O
General-purpose input/output.
SQCK
I
Servo SQCK or control.
AUX11
35
I/O
General-purpose input/output.
IRQ
I
ES3880 IRQ or interrupt output or control.
AUX12
36
I/O
General-purpose input/output.
C2PO
I
CD C2PO or interrupt input or control.
Table 1 ES3889 Pin Descriptions (Continued)
Names
Pin Numbers
I/O
Definitions
SEL_PLL1
SEL_PLL0
DCLK
0
Bypass PLL (input mode)
0
1
27 MHz (output mode)
1
0
32.4 MHz (output mode)
1
40.5 MHz (output mode)