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參數(shù)資料
| 型號： | ES2838S |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | V.90/V.92 PCI HSP Modem Product Brief |
| 中文描述： | 熱休克蛋白的PCI V.90/V.92調(diào)制解調(diào)器產(chǎn)品簡介 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 310K |
| 代理商： | ES2838S |
ESS Technology, Inc.
SAM0316-041101
3
ES2838 PRODUCT BRIEF
ES2838 PIN DESCRIPTIONS
Table 1 lists the ES2838 pin descriptions.
Table 1 ES2838 Pin Descriptions
Names
Pin Numbers
I/O
Definitions
C/BE3:0#
1, 13, 21, 31
I/O
Multiplexed bus command/byte enable. These pins indicate cycle type during the
address phase of a transaction. They indicate active-low byte enable information for the
current data phase during the data phases of a transaction. These pins are inputs during
slave operation and outputs during bus mastering operation.
IDSEL
2
I
Initialization device select, active-high. Used as a chip select during PCI configuration
read and write cycles.
GND
3, 15, 22, 41,
52, 61, 91
G
Digital ground.
VDD
12, 32, 46, 51,
58, 89, 100
P
Digital voltage [VDD (3.3V)].
AD31:0
4:11, 23:30,
33:40, 92:99
I/O
Address and data AD31:0.
FRAME#
14
I/O
Cycle frame, active-low. The current PCI bus master drives this pin to indicate the
beginning and duration of a transaction.
IRDY#
16
I/O
Initiator ready, active-low. The current PCI bus master drives this pin to indicate that as
the initiator it is ready to transmit or receive data (and complete the current data phase).
TRDY#
17
I/O
Target ready pin, active-low. The current PCI bus master drives this pin to indicate that
as the target device it is ready to transmit or receive data (and complete the current data
phase).
DEVSEL#
18
I/O
Device select, active-low. The PCI bus target device drives this pin to indicate that it has
decoded the address of the current transaction as its own chip select range.
STOP#
19
I/O
Stop transaction, active-low. The current PCI bus target drives this pin active to indicate
a request to the master to stop the current transaction.
PAR
20
I/O
Parity pin, active-high. Indicates even parity across AD[31:0] and C/BE[3:0]# for both
address and data phases. The signal is delayed one PCI clock from either the address
or data phase for which parity is generated.
SEDO
42
I
Serial EPROM data output pin with internal pullup.
SEDI
43
O
Serial EPROM data input pin.
SECLK
44
O
Serial EPROM data clock input pin with internal pulldown.
SECS
45
O
Serial EPROM port chip select pin with internal pulldown.
LCS / PF3
48
I
Local current sense input when selected.
PF[5:4] and
PF[2:1]
47, 49, 50, 64
I/O
General-purpose programmable bidirectional flag. Can be used for interfacing with a
telephone or other device, performing such functions as phone off-hook, phone on-hook,
ring, and caller ID.
CURLIM#
53
O
Current limit control output.
COMPLX#
54
O
Complex impedance select output.
DPBX#
55
I
Digital PBX detection input.
CLKRUN#
56
I/O
PCI clock state for power management.
DSPK
57
O
Modem speaker digital output.
PF11
O
General-purpose programable flag.
OSCI
59
I
18.816-MHz crystal oscillator input.
OSCO
60
O
18.816-MHz crystal oscillator output.
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