參數資料
型號: EPM9560RI240-20
廠商: Altera
文件頁數: 24/46頁
文件大?。?/td> 0K
描述: IC MAX 9000 CPLD 560 240-RQFP
產品變化通告: Package Change 30/Jun/2010
標準包裝: 24
系列: Max® 9000
可編程類型: 系統(tǒng)內可編程
最大延遲時間 tpd(1): 20.0ns
電壓電源 - 內部: 4.5 V ~ 5.5 V
邏輯元件/邏輯塊數目: 35
宏單元數: 560
門數: 12000
輸入/輸出數: 191
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 240-BFQFP 裸露焊盤
供應商設備封裝: 240-RQFP(32x32)
包裝: 托盤
其它名稱: 544-2367
30
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
Timing Model
The continuous, high-performance FastTrack Interconnect ensures
predictable performance and accurate simulation and timing analysis.
This predictable performance contrasts with that of FPGAs, which use a
segmented connection scheme and hence have unpredictable
performance. Timing simulation and delay prediction are available with
the MAX+PLUS II Simulator and Timing Analyzer, or with industry-
standard EDA tools. The Simulator offers both pre-synthesis functional
simulation to evaluate logic design accuracy and post-synthesis timing
simulation with 0.1-ns resolution. The Timing Analyzer provides point-
to-point timing delay information, setup and hold time prediction, and
device-wide performance analysis.
The MAX 9000 timing model in Figure 14 shows the delays that
correspond to various paths and functions in the circuit. This model
contains three distinct parts: the macrocell, IOC, and interconnect,
including the row and column FastTrack Interconnect and LAB local array
paths. Each parameter shown in Figure 14 is expressed as a worst-case
value in the internal timing characteristics tables in this data sheet. Hand-
calculations that use the MAX 9000 timing model and these timing
parameters can be used to estimate MAX 9000 device performance.
f For more information on calculating MAX 9000 timing delays, see
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EPM9560RI304-15 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
EPM9560RI304-20 制造商:Altera Corporation 功能描述:IC MAX
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