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參數(shù)資料

Altera Corporation

MAX 9000 Programmable Logic Device Family Data Sheet

Timing Model

The continuous, high-performance FastTrack Interconnect ensures

predictable performance and accurate simulation and timing analysis.

This predictable performance contrasts with that of FPGAs, which use a

segmented connection scheme and hence have unpredictable

performance. Timing simulation and delay prediction are available with

the MAX+PLUS II Simulator and Timing Analyzer, or with industry-

standard EDA tools. The Simulator offers both pre-synthesis functional

simulation to evaluate logic design accuracy and post-synthesis timing

simulation with 0.1-ns resolution. The Timing Analyzer provides point-

to-point timing delay information, setup and hold time prediction, and

device-wide performance analysis.

The MAX 9000 timing model in Figure 14 shows the delays that

correspond to various paths and functions in the circuit. This model

contains three distinct parts: the macrocell, IOC, and interconnect,

including the row and column FastTrack Interconnect and LAB local array

paths. Each parameter shown in Figure 14 is expressed as a worst-case

value in the internal timing characteristics tables in this data sheet. Hand-

calculations that use the MAX 9000 timing model and these timing

parameters can be used to estimate MAX 9000 device performance.

f For more information on calculating MAX 9000 timing delays, see

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
EPM9320BI356-15	制造商:未知廠家制造商全稱:未知廠家功能描述:
EPM9320BI356-20	制造商:未知廠家制造商全稱:未知廠家功能描述:
EPM9320GI280-15	制造商:未知廠家制造商全稱:未知廠家功能描述:
EPM9320GI280-20	制造商:未知廠家制造商全稱:未知廠家功能描述:
EPM9320LC84-15	功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 9000 320 Macro 60 IOs RoHS:否制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

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