參數(shù)資料
型號： EPM7512AEQC208-12
文件頁數(shù)： 60/60頁
文件大?。?/td> 1041K
代理商： EPM7512AEQC208-12
Altera Corporation
9
MAX 7000A Programmable Logic Device Data Sheet
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
Altera software then selects the most efficient flipflop operation for each
registered function to optimize resource utilization.
Each programmable register can be clocked in three different modes:
I
Global clock signal. This mode achieves the fastest clock-to-output
performance.
I
Global clock signal enabled by an active-high clock enable. A clock
enable is generated by a product term. This mode provides an enable
on each flipflop while still achieving the fast clock-to-output
performance of the global clock.
I
Array clock implemented with a product term. In this mode, the
flipflop can be clocked by signals from buried macrocells or I/O pins.
Two global clock signals are available in MAX 7000A devices. As shown
in Figure 1, these global clock signals can be the true or the complement
of either of the global clock pins, GCLK1 or GCLK2.
Each register also supports asynchronous preset and clear functions. As
shown in Figure 2, the product-term select matrix allocates product terms
to control these operations. Although the product-term-driven preset and
clear from the register are active high, active-low control can be obtained
by inverting the signal within the logic array. In addition, each register
clear function can be individually driven by the active-low dedicated
global clear pin (GCLRn). Upon power-up, each register in a MAX 7000AE
device may be set to either a high or low state. This power-up state is
specified at design entry. Upon power-up, each register in EPM7128A and
EPM7256A devices are set to a low state.
All MAX 7000A I/O pins have a fast input path to a macrocell register.
This dedicated path allows a signal to bypass the PIA and combinatorial
logic and be clocked to an input D flipflop with an extremely fast (as low
as 2.5 ns) input setup time.
相關PDF資料
PDF描述
EPM7512AEQC208-7
EPM7512AEQI208-10
EPM7512AETC144-10
EPM7512AETC144-12
EPM7512AETC144-7
相關代理商/技術參數(shù)
參數(shù)描述
EPM7512AEQC208-12N 功能描述:CPLD - 復雜可編程邏輯器件 CPLD - MAX 7000 512 Macro 176 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7512AEQC208-7 功能描述:CPLD - 復雜可編程邏輯器件 CPLD - MAX 7000 512 Macro 176 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7512AEQC208-7N 功能描述:CPLD - 復雜可編程邏輯器件 CPLD - MAX 7000 512 Macro 176 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7512AEQI208-10 功能描述:CPLD - 復雜可編程邏輯器件 CPLD - MAX 7000 512 Macro 176 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7512AEQI208-10N 功能描述:CPLD - 復雜可編程邏輯器件 CPLD - MAX 7000 512 Macro 176 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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