參數(shù)資料
型號： EPM7256AETI144-7N
廠商： Altera
文件頁數(shù)： 63/64頁
文件大?。?/td> 0K
描述： IC MAX 7000 CPLD 256 144-TQFP
產(chǎn)品變化通告： Bond Wire Change 4/Sept/2008
標(biāo)準(zhǔn)包裝： 180
系列： MAX® 7000A
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1)： 7.5ns
電壓電源 - 內(nèi)部： 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目： 16
宏單元數(shù)： 256
門數(shù)： 5000
輸入/輸出數(shù)： 120
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
包裝： 托盤
其它名稱： 544-2063
EPM7256AETI144-7N-ND
8
Altera Corporation
MAX 7000A Programmable Logic Device Data Sheet
Macrocells
MAX 7000A macrocells can be individually configured for either
sequential or combinatorial logic operation. The macrocells consist of
three functional blocks: the logic array, the product-term select matrix,
and the programmable register. Figure 2 shows a MAX 7000A macrocell.
Figure 2. MAX 7000A Macrocell
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the OR and
XOR
gates) to implement combinatorial functions, or as secondary inputs
to the macrocell’s register preset, clock, and clock enable control
functions.
Two kinds of expander product terms (“expanders”) are available to
supplement macrocell logic resources:
■
Shareable expanders, which are inverted product terms that are fed
back into the logic array
■
Parallel expanders, which are product terms borrowed from adjacent
macrocells
The Altera development system automatically optimizes product-term
allocation according to the logic requirements of the design.
Product-
Term
Select
Matrix
36 Signals
from PIA
16 Expander
Product Terms
LAB Local Array
Parallel Logic
Expanders
(from other
macrocells)
Shared Logic
Expanders
Clear
Select
Global
Clear
Global
Clocks
Clock/
Enable
Select
2
PRN
CLRN
D/T
Q
ENA
Register
Bypass
To I/O
Control
Block
From
I/O pin
To PIA
Programmable
Register
Fast Input
Select
VCC
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EPM7256AETI144-7 IC MAX 7000 CPLD 256 144-TQFP
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