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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� EPM7256AETC144-5
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 37/64闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MAX 7000 CPLD 256 144-TQFP
鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� Bond Wire Change 4/Sept/2008
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 180
绯诲垪锛� MAX® 7000A
鍙法绋嬮鍨嬶細 绯荤当(t菕ng)鍏�(n猫i)鍙法绋�
鏈€澶у欢閬叉檪(sh铆)闁� tpd(1)锛� 5.5ns
闆诲闆绘簮 - 鍏�(n猫i)閮細 3 V ~ 3.6 V
閭忚集鍏冧欢/閭忚集濉婃暩(sh霉)鐩細 16
瀹忓柈鍏冩暩(sh霉)锛� 256
闁€鏁�(sh霉)锛� 5000
杓稿叆/杓稿嚭鏁�(sh霉)锛� 120
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 144-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-TQFP锛�20x20锛�
鍖呰锛� 鎵樼洡
鍏跺畠鍚嶇ū锛� 544-2060
EPM7256AETC144-5-ND
42
Altera Corporation
MAX 7000A Programmable Logic Device Data Sheet
tEN
Register enable time
0.7
1.0
1.3
ns
tGLOB
Global control delay
1.1
1.6
2.0
ns
tPRE
Register preset time
1.4
2.0
2.7
ns
tCLR
Register clear time
1.4
2.0
2.7
ns
tPIA
PIA delay
1.4
2.0
2.6
ns
tLPA
Low-power adder
4.0
5.0
ns
Table 22. EPM7128AE Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-5
-7
-10
Min
Max
Min
Max
Min
Max
鐩搁棞(gu膩n)PDF璩囨枡
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
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