參數(shù)資料
型號(hào)： EPM7096
廠商： Altera Corporation
英文描述： Programmable Logic Device Family
中文描述： 可編程邏輯器件系列
文件頁(yè)數(shù)： 1/62頁(yè)
文件大小： 1173K
代理商： EPM7096
Altera Corporation
1
MAX 7000
Programmable Logic
Device Family
December 2002, ver. 6.5
Data Sheet
DS-MAX7000-6.5
Features...
■
High-performance, EEPROM-based programmable logic devices
(PLDs) based on second-generation MAX
architecture
5.0-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in
MAX 7000S devices
–
ISP circuitry compatible with IEEE Std. 1532
Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S
devices
Built-in JTAG boundary-scan test (BST) circuitry in MAX
7000S
devices with 128 or more macrocells
Complete EPLD family with logic densities ranging from 600 to
5,000 usable gates (see
Tables 1
and
2
)
5-ns pin-to-pin logic delays with up to 175.4-MHz counter
frequencies (including interconnect)
PCI-compliant devices available
■
■
■
■
■
■
f
For information on in-system programmable 3.3-V MAX 7000A or 2.5-V
MAX 7000A Programmable Logic Device Family
Sheet
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM7096JC68 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP Complex PLD
EPM7096JC68-2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP Complex PLD
EPM7096JC68-3 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP Complex PLD
EPM7096JC84 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP Complex PLD
EPM7096JC84-2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP Complex PLD
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