鍨嬭櫉锛� | EPM7064LC44-7 |
寤犲晢锛� | Altera |
鏂囦欢闋佹暩(sh霉)锛� | 42/66闋� |
鏂囦欢澶�?銆�?/td> | 0K |
鎻忚堪锛� | IC MAX 7000 CPLD 64 44-PLCC |
妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 390 |
绯诲垪锛� | MAX® 7000 |
鍙法绋嬮鍨嬶細 | 绯荤当(t菕ng)鍏�(n猫i)鍙法绋� |
鏈€澶у欢閬叉檪闁� tpd(1)锛� | 7.5ns |
闆诲闆绘簮 - 鍏�(n猫i)閮細 | 4.75 V ~ 5.25 V |
閭忚集鍏冧欢/閭忚集濉婃暩(sh霉)鐩細 | 4 |
瀹忓柈鍏冩暩(sh霉)锛� | 64 |
闁€鏁�(sh霉)锛� | 1250 |
杓稿叆/杓稿嚭鏁�(sh霉)锛� | 36 |
宸ヤ綔婧害锛� | 0°C ~ 70°C |
瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
灏佽/澶栨锛� | 44-LCC锛圝 褰㈠紩绶氾級 |
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 44-PLCC锛�16.58x16.58锛� |
鍖呰锛� | 绠′欢 |
鍏跺畠鍚嶇ū锛� | 544-2299-5 |
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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MAX6502UKP115+T | IC TEMP SWITCH SOT23-5 |
RCM03DRUN | CONN EDGECARD 6POS DIP .156 SLD |
RCB45DHBT | CONN EDGECARD 90POS R/A .050 DIP |
EYM10DRSH | CONN EDGECARD 20POS DIP .156 SLD |
EEM24DRXI | CONN EDGECARD 48POS DIP .156 SLD |
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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EPM7064LC44-7N | 鍒堕€犲晢:Altera Corporation 鍔熻兘鎻忚堪:CPLD MAX 7000 Family 1.25K Gates 64 Macro Cells 125MHz CMOS Technology 5V 44-Pin PLCC |
EPM7064LC44-7YY | 鍒堕€犲晢:Altera Corporation 鍔熻兘鎻忚堪:CPLD MAX 7000 Family 1.25K Gates 64 Macro Cells 125MHz CMOS Technology 5V 44-Pin PLCC |
EPM7064LC5815 | 鍒堕€犲晢:Altera Corporation 鍔熻兘鎻忚堪: |
EPM7064LC68-10 | 鍔熻兘鎻忚堪:CPLD - 寰�(f霉)闆滃彲绶ㄧ▼閭忚集鍣ㄤ欢 CPLD - MAX 7000 64 Macro 52 IOs RoHS:鍚� 鍒堕€犲晢:Lattice 绯诲垪: 瀛樺劜椤炲瀷:EEPROM 澶ч浕姹犳暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:333 MHz 寤堕伈鏅傞枔:2.7 ns 鍙法绋嬭几鍏�/杓稿嚭绔暩(sh霉)閲�:64 宸ヤ綔闆绘簮闆诲:3.3 V 鏈€澶у伐浣滄韩搴�:+ 90 C 鏈€灏忓伐浣滄韩搴�:0 C 灏佽 / 绠遍珨:TQFP-100 |
EPM7064LC68-12 | 鍔熻兘鎻忚堪:CPLD - 寰�(f霉)闆滃彲绶ㄧ▼閭忚集鍣ㄤ欢 CPLD - MAX 7000 64 Macro 52 IOs RoHS:鍚� 鍒堕€犲晢:Lattice 绯诲垪: 瀛樺劜椤炲瀷:EEPROM 澶ч浕姹犳暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:333 MHz 寤堕伈鏅傞枔:2.7 ns 鍙法绋嬭几鍏�/杓稿嚭绔暩(sh霉)閲�:64 宸ヤ綔闆绘簮闆诲:3.3 V 鏈€澶у伐浣滄韩搴�:+ 90 C 鏈€灏忓伐浣滄韩搴�:0 C 灏佽 / 绠遍珨:TQFP-100 |