參數(shù)資料
型號: EPM7064BFC100-3
廠商: Altera
文件頁數(shù): 19/66頁
文件大小: 0K
描述: IC MAX 7000 CPLD 64 100-FBGA
標(biāo)準(zhǔn)包裝: 176
系列: MAX® 7000B
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 3.5ns
電壓電源 - 內(nèi)部: 2.375 V ~ 2.625 V
邏輯元件/邏輯塊數(shù)目: 4
宏單元數(shù): 64
門數(shù): 1250
輸入/輸出數(shù): 68
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LBGA
供應(yīng)商設(shè)備封裝: 100-FBGA(11x11)
包裝: 托盤
26
Altera Corporation
MAX 7000B Programmable Logic Device Data Sheet
Two inverters implement the bus-hold circuitry in a loop that weakly
drives back to the I/O pin in user mode.
Figure 10 shows a block diagram of the bus-hold circuit.
Figure 10. Bus-Hold Circuit
PCI
Compatibility
MAX 7000B devices are compatible with PCI applications as well as all
3.3-V electrical specifications in the PCI Local Bus Specification
Revision 2.2
except for the clamp diode. While having multiple clamp
diodes on a signal trace may be redundant, designers can add an external
clamp diode to meet the specification. Table 13 shows the MAX 7000B
device speed grades that meet the PCI timing specifications.
Note:
(1)
The EPM7256B and EPM7512B devices in a -5 speed grade meet all PCI timing
specifications for 66-MHz operation except the Input Setup Time to CLK—Bused
Signal parameter. However, these devices are within 1 ns of that parameter.
EPM7256B and EPM7512B devices meet all other 66-MHz PCI timing
specifications.
I/O
RBH
Bus Hold Circuit
Drive to
VCCIO level
Table 13. MAX 7000B Device Speed Grades that Meet PCI Timing
Specifications
Device
Specification
33-MHz PCI
66-MHz PCI
EPM7032B
All speed grades
-3
EPM7064B
All speed grades
-3
EPM7128B
All speed grades
-4
EPM7256B
All speed grades
-5 (1)
EPM7512B
All speed grades
-5 (1)
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