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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� EPM7064AETC100-4N
寤犲晢锛� Altera
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 43/64闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC MAX 7000 CPLD 64 100-TQFP
鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� Bond Wire Change 4/Sept/2008
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 270
绯诲垪锛� MAX® 7000A
鍙法绋嬮鍨嬶細 绯荤当(t菕ng)鍏�(n猫i)鍙法绋�
鏈€澶у欢閬叉檪(sh铆)闁� tpd(1)锛� 4.5ns
闆诲闆绘簮 - 鍏�(n猫i)閮細 3 V ~ 3.6 V
閭忚集鍏冧欢/閭忚集濉婃暩(sh霉)鐩細 4
瀹忓柈鍏冩暩(sh霉)锛� 64
闁€鏁�(sh霉)锛� 1250
杓稿叆/杓稿嚭鏁�(sh霉)锛� 68
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 100-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 100-TQFP锛�14x14锛�
鍖呰锛� 鎵樼洡
鍏跺畠鍚嶇ū锛� 544-2580
EPM7064AETC100-4N-ND
48
Altera Corporation
MAX 7000A Programmable Logic Device Data Sheet
tIC
Array clock delay
1.8
2.3
2.9
ns
tEN
Register enable time
1.0
1.3
1.7
ns
tGLOB
Global control delay
1.7
2.2
2.7
ns
tPRE
Register preset time
1.0
1.4
1.7
ns
tCLR
Register clear time
1.0
1.4
1.7
ns
tPIA
PIA delay
3.0
4.0
4.8
ns
tLPA
Low-power adder
4.5
5.0
ns
Table 26. EPM7512AE Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-7
-10
-12
Min
Max
Min
Max
Min
Max
鐩搁棞(gu膩n)PDF璩囨枡
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鍙冩暩(sh霉)鎻忚堪
EPM7064AETC100-5 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:Electrically-Erasable Complex PLD
EPM7064AETC1007 鍒堕€犲晢:Altera Corporation 鍔熻兘鎻忚堪:
EPM7064AETC100-7 鍔熻兘鎻忚堪:CPLD - 寰�(f霉)闆滃彲绶ㄧ▼閭忚集鍣ㄤ欢 CPLD - MAX 7000 64 Macro 68 IOs RoHS:鍚� 鍒堕€犲晢:Lattice 绯诲垪: 瀛樺劜(ch菙)椤炲瀷:EEPROM 澶ч浕姹�?c谩i)?sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:333 MHz 寤堕伈鏅�(sh铆)闁�:2.7 ns 鍙法绋嬭几鍏�/杓稿嚭绔暩(sh霉)閲�:64 宸ヤ綔闆绘簮闆诲:3.3 V 鏈€澶у伐浣滄韩搴�:+ 90 C 鏈€灏忓伐浣滄韩搴�:0 C 灏佽 / 绠遍珨:TQFP-100
EPM7064AETC100-7N 鍔熻兘鎻忚堪:CPLD - 寰�(f霉)闆滃彲绶ㄧ▼閭忚集鍣ㄤ欢 CPLD - MAX 7000 64 Macro 68 IOs RoHS:鍚� 鍒堕€犲晢:Lattice 绯诲垪: 瀛樺劜(ch菙)椤炲瀷:EEPROM 澶ч浕姹�?c谩i)?sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:333 MHz 寤堕伈鏅�(sh铆)闁�:2.7 ns 鍙法绋嬭几鍏�/杓稿嚭绔暩(sh霉)閲�:64 宸ヤ綔闆绘簮闆诲:3.3 V 鏈€澶у伐浣滄韩搴�:+ 90 C 鏈€灏忓伐浣滄韩搴�:0 C 灏佽 / 绠遍珨:TQFP-100
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