tACNT Minimum array clock pe" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EPM7032SLI44-7N
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 42/66闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC MAX 7000 CPLD 32 44-PLCC
鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� MAX 7000 Series Obsolescence 08/Jun/2009
妯欐簴鍖呰锛� 390
绯诲垪锛� MAX® 7000
鍙法绋嬮鍨嬶細 绯荤当(t菕ng)鍏у彲绶ㄧ▼
鏈€澶у欢閬叉檪闁� tpd(1)锛� 7.5ns
闆诲闆绘簮 - 鍏ч儴锛� 4.5 V ~ 5.5 V
閭忚集鍏冧欢/閭忚集濉婃暩(sh霉)鐩細 2
瀹忓柈鍏冩暩(sh霉)锛� 32
闁€鏁�(sh霉)锛� 600
杓稿叆/杓稿嚭鏁�(sh霉)锛� 36
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 44-LCC锛圝 褰㈠紩绶氾級
渚涙噳鍟嗚ō鍌欏皝瑁濓細 44-PLCC锛�16.58x16.58锛�
鍖呰锛� 绠′欢
鍏跺畠鍚嶇ū锛� 544-2003
EPM7032SLI44-7N-ND
Altera Corporation
47
MAX 7000 Programmable Logic Device Family Data Sheet
tACNT
Minimum array clock period
6.7
8.2
10.0
13.0
ns
fACNT
Maximum internal array clock
frequency
149.3
122.0
100.0
76.9
MHz
fMAX
Maximum clock frequency
166.7
125.0
100.0
MHz
Table 34. EPM7160S Internal Timing Parameters (Part 1 of 2)
Symbol
Parameter
Conditions
Speed Grade
Unit
-6
-7
-10
-15
Min
Max
Min
Max
Min
Max
Min
Max
tIN
Input pad and buffer delay
0.2
0.3
0.5
2.0
ns
tIO
I/O input pad and buffer delay
0.2
0.3
0.5
2.0
ns
tFIN
Fast input delay
2.6
3.2
1.0
2.0
ns
tSEXP
Shared expander delay
3.6
4.3
5.0
8.0
ns
tPEXP
Parallel expander delay
1.0
1.3
0.8
1.0
ns
tLAD
Logic array delay
2.8
3.4
5.0
6.0
ns
tLAC
Logic control array delay
2.8
3.4
5.0
6.0
ns
tIOE
Internal output enable delay
0.7
0.9
2.0
3.0
ns
tOD1
Output buffer and pad delay
C1 = 35 pF
0.4
0.5
1.5
4.0
ns
tOD2
Output buffer and pad delay
C1 = 35 pF (6)
0.9
1.0
2.0
5.0
ns
tOD3
Output buffer and pad delay
C1 = 35 pF
5.4
5.5
8.0
ns
tZX1
Output buffer enable delay
C1 = 35 pF
4.0
5.0
6.0
ns
tZX2
Output buffer enable delay
C1 = 35 pF (6)
4.5
5.5
7.0
ns
tZX3
Output buffer enable delay
C1 = 35 pF
9.0
10.0
ns
tXZ
Output buffer disable delay
C1 = 5 pF
4.0
5.0
6.0
ns
tSU
Register setup time
1.0
1.2
2.0
4.0
ns
tH
Register hold time
1.6
2.0
3.0
4.0
ns
tFSU
Register setup time of fast
input
1.9
2.2
3.0
2.0
ns
tFH
Register hold time of fast
input
0.6
0.8
0.5
1.0
ns
tRD
Register delay
1.3
1.6
2.0
1.0
ns
tCOMB
Combinatorial delay
1.0
1.3
2.0
1.0
ns
tIC
Array clock delay
2.9
3.5
5.0
6.0
ns
tEN
Register enable time
2.8
3.4
5.0
6.0
ns
tGLOB
Global control delay
2.0
2.4
1.0
ns
tPRE
Register preset time
2.4
3.0
4.0
ns
Table 33. EPM7160S External Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-6
-7
-10
-15
MinMax MinMax MinMax MinMax
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鎴戠殑鑱�(li谩n)绯绘柟寮�

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