f For more information on using " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EPM7032SLC44-6N
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 9/66闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC MAX 7000 CPLD 32 44-PLCC
鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� MAX 7000 Series Obsolescence 08/Jun/2009
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 390
绯诲垪锛� MAX® 7000
鍙法绋嬮鍨嬶細 绯荤当(t菕ng)鍏�(n猫i)鍙法绋�
鏈€澶у欢閬叉檪(sh铆)闁� tpd(1)锛� 6.0ns
闆诲闆绘簮 - 鍏�(n猫i)閮細 4.75 V ~ 5.25 V
閭忚集鍏冧欢/閭忚集濉婃暩(sh霉)鐩細 2
瀹忓柈鍏冩暩(sh霉)锛� 32
闁€鏁�(sh霉)锛� 600
杓稿叆/杓稿嚭鏁�(sh霉)锛� 36
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 44-LCC锛圝 褰㈠紩绶氾級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 44-PLCC锛�16.58x16.58锛�
鍖呰锛� 绠′欢
Altera Corporation
17
MAX 7000 Programmable Logic Device Family Data Sheet
f For more information on using the Jam language, refer to AN 122: Using
Jam STAPL for ISP & ICR via an Embedded Processor.
The ISP circuitry in MAX 7000S devices is compatible with IEEE Std. 1532
specification. The IEEE Std. 1532 is a standard developed to allow
concurrent ISP between multiple PLD vendors.
Programming Sequence
During in-system programming, instructions, addresses, and data are
shifted into the MAX 7000S device through the TDI input pin. Data is
shifted out through the TDO output pin and compared against the
expected data.
Programming a pattern into the device requires the following six ISP
stages. A stand-alone verification of a programmed pattern involves only
stages 1, 2, 5, and 6.
1.
Enter ISP. The enter ISP stage ensures that the I/O pins transition
smoothly from user mode to ISP mode. The enter ISP stage requires
1ms.
2.
Check ID. Before any program or verify process, the silicon ID is
checked. The time required to read this silicon ID is relatively small
compared to the overall programming time.
3.
Bulk Erase. Erasing the device in-system involves shifting in the
instructions to erase the device and applying one erase pulse of
100 ms.
4.
Program. Programming the device in-system involves shifting in the
address and data and then applying the programming pulse to
program the EEPROM cells. This process is repeated for each
EEPROM address.
5.
Verify. Verifying an Altera device in-system involves shifting in
addresses, applying the read pulse to verify the EEPROM cells, and
shifting out the data for comparison. This process is repeated for
each EEPROM address.
6.
Exit ISP. An exit ISP stage ensures that the I/O pins transition
smoothly from ISP mode to user mode. The exit ISP stage requires
1ms.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
EPM7032SLC44-7 鍔熻兘鎻忚堪:IC MAX 7000 CPLD 32 44-PLCC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - CPLD锛堝京(f霉)闆滃彲绶ㄧ▼閭忚集鍣ㄤ欢锛� 绯诲垪:MAX® 7000 妯�(bi膩o)婧�(zh菙n)鍖呰:24 绯诲垪:CoolRunner II 鍙法绋嬮鍨�:绯荤当(t菕ng)鍏�(n猫i)鍙法绋� 鏈€澶у欢閬叉檪(sh铆)闁� tpd(1):7.1ns 闆诲闆绘簮 - 鍏�(n猫i)閮�:1.7 V ~ 1.9 V 閭忚集鍏冧欢/閭忚集濉婃暩(sh霉)鐩�:24 瀹忓柈鍏冩暩(sh霉):384 闁€鏁�(sh霉):9000 杓稿叆/杓稿嚭鏁�(sh霉):173 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:208-BFQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:208-PQFP锛�28x28锛� 鍖呰:鎵樼洡
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EPM7032SLI44-7N 鍔熻兘鎻忚堪:IC MAX 7000 CPLD 32 44-PLCC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - CPLD锛堝京(f霉)闆滃彲绶ㄧ▼閭忚集鍣ㄤ欢锛� 绯诲垪:MAX® 7000 妯�(bi膩o)婧�(zh菙n)鍖呰:24 绯诲垪:CoolRunner II 鍙法绋嬮鍨�:绯荤当(t菕ng)鍏�(n猫i)鍙法绋� 鏈€澶у欢閬叉檪(sh铆)闁� tpd(1):7.1ns 闆诲闆绘簮 - 鍏�(n猫i)閮�:1.7 V ~ 1.9 V 閭忚集鍏冧欢/閭忚集濉婃暩(sh霉)鐩�:24 瀹忓柈鍏冩暩(sh霉):384 闁€鏁�(sh霉):9000 杓稿叆/杓稿嚭鏁�(sh霉):173 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:208-BFQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:208-PQFP锛�28x28锛� 鍖呰:鎵樼洡
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