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參數(shù)資料
| 型號(hào)： | EPM3512AQI208-10 |
| 廠商： | Altera |
| 文件頁數(shù)： | 44/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MAX 3000A CPLD 512 208-PQFP |
| 標(biāo)準(zhǔn)包裝： | 72 |
| 系列： | MAX® 3000A |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時(shí)間 tpd(1)： | 10.0ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 邏輯元件/邏輯塊數(shù)目： | 32 |
| 宏單元數(shù)： | 512 |
| 門數(shù)： | 10000 |
| 輸入/輸出數(shù)： | 172 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
| 包裝： | 托盤 |
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Altera Corporation
7
MAX 3000A Programmable Logic Device Family Data Sheet
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
Altera development system software then selects the most efficient
flipflop operation for each registered function to optimize resource
utilization.
Each programmable register can be clocked in three different modes:
■
Global clock signal mode, which achieves the fastest clock–to–output
performance.
■
Global clock signal enabled by an active–high clock enable. A clock
enable is generated by a product term. This mode provides an enable
on each flipflop while still achieving the fast clock–to–output
performance of the global clock.
■
Array clock implemented with a product term. In this mode, the
flipflop can be clocked by signals from buried macrocells or I/O pins.
Two global clock signals are available in MAX 3000A devices. As shown
in Figure 1, these global clock signals can be the true or the complement of
either of the two global clock pins, GCLK1 or GCLK2.
Each register also supports asynchronous preset and clear functions. As
shown in Figure 2, the product–term select matrix allocates product terms
to control these operations. Although the product–term–driven preset
and clear from the register are active high, active–low control can be
obtained by inverting the signal within the logic array. In addition, each
register clear function can be individually driven by the active–low
dedicated global clear pin (GCLRn).
All registers are cleared upon power-up. By default, all registered outputs
drive low when the device is powered up. You can set the registered
outputs to drive high upon power-up through the Quartus II software.
Quartus II software uses the NOT Gate Push-Back method, which uses an
additional macrocell to set the output high. To set this in the Quartus II
software, go to the Assignment Editor and set the Power-Up Level
assignment for the register to High.
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| EPM3512AQI208-10N | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 3000A 512 Macro 172 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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