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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | EPM3128ATC100-7N |
| 寤犲晢锛� | Altera |
| 鏂囦欢闋佹暩(sh霉)锛� | 17/46闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC MAX 3000A CPLD 128 100-TQFP |
| 鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� | Bond Wire Change 4/Sept/2008 |
| 妯欐簴鍖呰锛� | 270 |
| 绯诲垪锛� | MAX® 3000A |
| 鍙法绋嬮鍨嬶細 | 绯荤当(t菕ng)鍏�(n猫i)鍙法绋� |
| 鏈€澶у欢閬叉檪闁� tpd(1)锛� | 7.5ns |
| 闆诲闆绘簮 - 鍏�(n猫i)閮細 | 3 V ~ 3.6 V |
| 閭忚集鍏冧欢/閭忚集濉婃暩(sh霉)鐩細 | 8 |
| 瀹忓柈鍏冩暩(sh霉)锛� | 128 |
| 闁€鏁�(sh霉)锛� | 2500 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 80 |
| 宸ヤ綔婧害锛� | 0°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 100-TQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 100-TQFP锛�14x14锛� |
| 鍖呰锛� | 鎵樼洡 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 603 (CN2011-ZH PDF) |
| 鍏跺畠鍚嶇ū锛� | 544-1983 EPM3128ATC100-7N-ND |
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24
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
(2)
Minimum DC input voltage is 鈥�0.5 V. During transitions, the inputs may undershoot to 鈥�2.0 V or overshoot to
5.75 V for input currents less than 100 mA and periods shorter than 20 ns.
(3)
All pins, including dedicated inputs, I/O pins, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(4)
These values are specified under the recommended operating conditions, as shown in Table 13 on page 23.
(5)
The parameter is measured with 50% of the outputs each sourcing the specified current. The IOH parameter refers
to high鈥搇evel TTL or CMOS output current.
(6)
The parameter is measured with 50% of the outputs each sinking the specified current. The IOL parameter refers to
low鈥搇evel TTL, PCI, or CMOS output current.
(7)
This value is specified during normal device operation. During power-up, the maximum leakage current is
卤300
渭A.
(8)
This pull鈥搖p exists while devices are programmed in鈥搒ystem and in unprogrammed devices during power鈥搖p.
(9)
Capacitance is measured at 25
掳 C and is sample鈥搕ested only. The OE1 pin (high鈥搗oltage pin during programming)
has a maximum capacitance of 20 pF.
(10) The POR time for all MAX 3000A devices does not exceed 100
渭s. The sufficient VCCINT voltage level for POR is
3.0 V. The device is fully initialized within the POR time after VCCINT reaches the sufficient POR voltage level.
(11) These devices support in-system programming for 鈥�40掳 to 100掳 C. For in-system programming support between 鈥�40掳
and 0掳 C, contact Altera Applications.
Figure 9 shows the typical output drive characteristics of MAX 3000A
devices.
Table 15. MAX 3000A Device Capacitance
Symbol
Parameter
Conditions
Min
Max
Unit
CIN
Input pin capacitance
VIN = 0 V, f = 1.0 MHz
8
pF
CI/O
I/O pin capacitance
VOUT = 0 V, f = 1.0 MHz
8
pF
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| EPM3128ATC144-10 | 鍔熻兘鎻忚堪:CPLD - 寰�(f霉)闆滃彲绶ㄧ▼閭忚集鍣ㄤ欢 CPLD - MAX 3000A 128 Macro 96 IOs RoHS:鍚� 鍒堕€犲晢:Lattice 绯诲垪: 瀛樺劜椤炲瀷:EEPROM 澶ч浕姹犳暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:333 MHz 寤堕伈鏅傞枔:2.7 ns 鍙法绋嬭几鍏�/杓稿嚭绔暩(sh霉)閲�:64 宸ヤ綔闆绘簮闆诲:3.3 V 鏈€澶у伐浣滄韩搴�:+ 90 C 鏈€灏忓伐浣滄韩搴�:0 C 灏佽 / 绠遍珨:TQFP-100 |
| EPM3128ATC144-10N | 鍔熻兘鎻忚堪:CPLD - 寰�(f霉)闆滃彲绶ㄧ▼閭忚集鍣ㄤ欢 CPLD - MAX 3000A 128 Macro 96 IOs RoHS:鍚� 鍒堕€犲晢:Lattice 绯诲垪: 瀛樺劜椤炲瀷:EEPROM 澶ч浕姹犳暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:333 MHz 寤堕伈鏅傞枔:2.7 ns 鍙法绋嬭几鍏�/杓稿嚭绔暩(sh霉)閲�:64 宸ヤ綔闆绘簮闆诲:3.3 V 鏈€澶у伐浣滄韩搴�:+ 90 C 鏈€灏忓伐浣滄韩搴�:0 C 灏佽 / 绠遍珨:TQFP-100 |
| EPM3128ATC1445 | 鍒堕€犲晢:ALTERA 鍔熻兘鎻忚堪:* |
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| EPM3128ATC144-5N | 鍔熻兘鎻忚堪:CPLD - 寰�(f霉)闆滃彲绶ㄧ▼閭忚集鍣ㄤ欢 CPLD - MAX 3000A 128 Macro 96 IOs RoHS:鍚� 鍒堕€犲晢:Lattice 绯诲垪: 瀛樺劜椤炲瀷:EEPROM 澶ч浕姹犳暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:333 MHz 寤堕伈鏅傞枔:2.7 ns 鍙法绋嬭几鍏�/杓稿嚭绔暩(sh霉)閲�:64 宸ヤ綔闆绘簮闆诲:3.3 V 鏈€澶у伐浣滄韩搴�:+ 90 C 鏈€灏忓伐浣滄韩搴�:0 C 灏佽 / 绠遍珨:TQFP-100 |
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