參數(shù)資料
型號: EPM3128ATC100-5
英文描述: Electrically-Erasable Complex PLD
中文描述: 電可擦除復(fù)雜可編程邏輯器件
文件頁數(shù): 13/53頁
文件大小: 839K
代理商: EPM3128ATC100-5
20
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
(2)
Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to
5.75 V for input currents less than 100 mA and periods shorter than 20 ns.
(3)
All pins, including dedicated inputs, I/O pins, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(4)
These values are specified under the recommended operating conditions, as shown in Table 10 on page 19.
(5)
The parameter is measured with 50% of the outputs each sourcing the specified current. The IOH parameter refers
to high-level TTL or CMOS output current.
(6)
The parameter is measured with 50% of the outputs each sinking the specified current. The IOL parameter refers to
low-level TTL or CMOS output current.
(7)
This pull-up exists while devices are programmed in-system and in unprogrammed devices during power-up.
(8)
Capacitance is measured at 25
° C and is sample-tested only. The OE1 pin (high-voltage pin during programming)
has a maximum capacitance of 20 pF.
Figure 9 shows the typical output drive characteristics of MAX 3000A
devices.
Table 12. MAX 3000A Device Capacitance
Symbol
Parameter
Conditions
Min
Max
Unit
CIN
Input pin capacitance
VIN = 0 V, f = 1.0 MHz
8
pF
CI/O
I/O pin capacitance
VOUT = 0 V, f = 1.0 MHz
8
pF
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