參數資料
型號： EPF8452ATC100-4N
廠商： Altera
文件頁數： 27/62頁
文件大?。?/td> 0K
描述： IC FLEX 8000 FPGA 4K 100-TQFP
產品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 270
系列： FLEX 8000
LAB/CLB數： 42
邏輯元件/單元數： 336
輸入/輸出數： 68
門數： 4000
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 100-TQFP
供應商設備封裝： 100-TQFP（14x14）
其它名稱： 544-1783
Altera Corporation
33
FLEX 8000 Programmable Logic Device Family Data Sheet
FL
EX
800
0
3
Table 17. FLEX 8000 Internal Timing Parameters
Symbol
Parameter
t IOD
IOE register data delay
t IOC
IOE register control signal delay
t IOE
Output enable delay
t IOCO
IOE register clock-to-output delay
t IOCOMB
IOE combinatorial delay
t IOSU
IOE register setup time before clock; IOE register recovery time after asynchronous clear
t IOH
IOE register hold time after clock
t IOCLR
IOE register clear delay
t IN
Input pad and buffer delay
t OD1
Output buffer and pad delay, slow slew rate = off, VCCIO = 5.0 V C1 = 35 pF (2)
t OD2
Output buffer and pad delay, slow slew rate = off, VCCIO = 3.3 V C1 = 35 pF (2)
t OD3
Output buffer and pad delay, slow slew rate = on, C1 = 35 pF (3)
t XZ
Output buffer disable delay, C1 = 5 pF
t ZX1
Output buffer enable delay, slow slew rate = off, VCCIO = 5.0 V, C1 = 35 pF (2)
t ZX2
Output buffer enable delay, slow slew rate = off, VCCIO = 3.3 V, C1 = 35 pF (2)
t ZX3
Output buffer enable delay, slow slew rate = on, C1 = 35 pF (3)
Table 18. FLEX 8000 LE Timing Parameters
Symbol
Parameter
t LUT
LUT delay for data-in
t CLUT
LUT delay for carry-in
t RLUT
LUT delay for LE register feedback
t GATE
Cascade gate delay
t CASC
Cascade chain routing delay
t CICO
Carry-in to carry-out delay
t CGEN
Data-in to carry-out delay
t CGENR
LE register feedback to carry-out delay
t C
LE register control signal delay
t CH
LE register clock high time
t CL
LE register clock low time
t CO
LE register clock-to-output delay
t COMB
Combinatorial delay
t SU
LE register setup time before clock; LE register recovery time after asynchronous preset, clear, or
load
t H
LE register hold time after clock
t PRE
LE register preset delay
t CLR
LE register clear delay
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