Notes to tables: (1) Microparameters are timing delays contributed " />
鍙冩暩(sh霉)璩囨枡
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寤犲晢锛� Altera
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Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
Microparameters are timing delays contributed by individual architectural elements and cannot be measured
explicitly.
(2)
Operating conditions:
VCCIO = 5.0 V 卤5% for commercial use in 5.0-V FLEX 6000 devices.
VCCIO = 5.0 V 卤10% for industrial use in 5.0-V FLEX 6000 devices.
VCCIO = 3.3 V 卤10% for commercial or industrial use in 3.3-V FLEX 6000 devices.
(3)
Operating conditions:
VCCIO = 3.3 V 卤10% for commercial or industrial use in 5.0-V FLEX 6000 devices.
VCCIO = 2.5 V 卤0.2 V for commercial or industrial use in 3.3-V FLEX 6000 devices.
(4)
Operating conditions:
VCCIO = 2.5 V, 3.3 V, or 5.0 V.
(5)
These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing
analysis are required to determine actual worst-case performance.
(6)
This timing parameter shows the delay of a register-to-register test pattern and is used to determine speed grades.
There are 12 LEs, including source and destination registers. The row and column interconnects between the
registers vary in length.
(7)
This timing parameter is shown for reference and is specified by characterization.
(8)
This timing parameter is specified by characterization.
Tables 24 through 28 show the timing information for EPF6010A and
EPF6016A devices.
Table 23. External Timing Parameters
Symbol
Parameter
Conditions
tINSU
Setup time with global clock at LE register
tINH
Hold time with global clock at LE register
tOUTCO
Clock-to-output delay with global clock with LE register using FastFLEX I/O
pin
Table 24. LE Timing Microparameters for EPF6010A & EPF6016A Devices (Part 1 of 2)
Parameter
Speed Grade
Unit
-1
-2
-3
Min
Max
Min
Max
Min
Max
tREG_TO_REG
1.2
1.3
1.7
ns
tCASC_TO_REG
0.9
1.0
1.2
ns
tCARRY_TO_REG
0.9
1.0
1.2
ns
tDATA_TO_REG
1.1
1.2
1.5
ns
tCASC_TO_OUT
1.3
1.4
1.8
ns
tCARRY_TO_OUT
1.6
1.8
2.3
ns
tDATA_TO_OUT
1.7
2.0
2.5
ns
tREG_TO_OUT
0.4
0.5
ns
tSU
0.9
1.0
1.3
ns
tH
1.4
1.7
2.1
ns
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