參數(shù)資料
型號： EPF10K50VRC240-3N
廠商： Altera
文件頁數(shù)： 61/128頁
文件大?。?/td> 0K
描述： IC FLEX 10KV FPGA 50K 240-RQFP
產品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
產品變化通告： Package Change 30/Jun/2010
標準包裝： 24
系列： FLEX-10K®
LAB/CLB數(shù)： 360
邏輯元件/單元數(shù)： 2880
RAM 位總計： 20480
輸入/輸出數(shù)： 189
門數(shù)： 116000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 240-BFQFP 裸露焊盤
供應商設備封裝： 240-RQFP（32x32）
38
Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Figure 17. Enabling ClockLock & ClockBoost in the Same Design
To use both the ClockLock and ClockBoost circuits in the same design,
designers must use Revision C EPF10K100GC503-3DX devices and
MAX+PLUS II software versions 7.2 or higher. The die revision is
indicated by the third digit of the nine-digit code on the top side of the
device.
Output
Configuration
This section discusses the peripheral component interconnect (PCI)
pull-up clamping diode option, slew-rate control, open-drain output
option, MultiVolt I/O interface, and power sequencing for FLEX 10K
devices. The PCI pull-up clamping diode, slew-rate control, and
open-drain output options are controlled pin-by-pin via Altera logic
options. The MultiVolt I/O interface is controlled by connecting VCCIO to
a different voltage than VCCINT. Its effect can be simulated in the Altera
software via the Global Project Device Options dialog box (Assign
menu).
PCI Clamping Diodes
The EPF10K10A and EPF10K30A devices have a pull-up clamping diode
on every I/O, dedicated input, and dedicated clock pin. PCI clamping
diodes clamp the transient overshoot caused by reflected waves to the
VCCIO value and are required for 3.3-V PCI compliance. Clamping diodes
can also be used to limit overshoot in other systems.
Clamping diodes are controlled on a pin-by-pin basis via a logic option in
the Altera software. When VCCIO is 3.3 V, a pin that has the clamping
diode turned on can be driven by a 2.5-V or 3.3-V signal, but not a 5.0-V
signal. When VCCIO is 2.5 V, a pin that has the clamping diode turned on
can be driven by a 2.5-V signal, but not a 3.3-V or 5.0-V signal. However,
a clamping diode can be turned on for a subset of pins, which allows
devices to bridge between a 3.3-V PCI bus and a 5.0-V device.
DQ
a
b
aout
bout
gclk1
CLKLOCK
CLOCKBOOST=1
INPUT_FREQUENCY=50
CLOCKBOOST=2
INPUT_FREQUENCY=50
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相關代理商/技術參數(shù)
參數(shù)描述
EPF10K50VRC240-4 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 360 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K50VRC240-4N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 360 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K50VRI240-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 360 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K50VRI240-3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 360 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K50VRI240-4 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 360 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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