參數資料
    型號: EPF10K30EQI208-1DX
    英文描述: ASIC
    中文描述: 專用集成電路
    文件頁數: 28/120頁
    文件大小: 1901K
    代理商: EPF10K30EQI208-1DX
    Altera Corporation
    15
    FLEX 10KE Embedded Programmable Logic Family Data Sheet
    EABs provide flexible options for driving and controlling clock signals.
    Different clocks and clock enables can be used for reading and writing to
    the EAB. Registers can be independently inserted on the data input, EAB
    output, write address, write enable signals, read address, and read enable
    signals. The global signals and the EAB local interconnect can drive write
    enable, read enable, and clock enable signals. The global signals,
    dedicated clock pins, and EAB local interconnect can drive the EAB clock
    signals. Because the LEs drive the EAB local interconnect, the LEs can
    control write enable, read enable, clear, clock, and clock enable signals.
    An EAB is fed by a row interconnect and can drive out to row and column
    interconnects. Each EAB output can drive up to two row channels and up
    to two column channels; the unused row channel can be driven by other
    LEs. This feature increases the routing resources available for EAB
    outputs (see Figures 2 and 4). The column interconnect, which is adjacent
    to the EAB, has twice as many channels as other columns in the device.
    Logic Array Block
    An LAB consists of eight LEs, their associated carry and cascade chains,
    LAB control signals, and the LAB local interconnect. The LAB provides
    the coarse-grained structure to the FLEX 10KE architecture, facilitating
    efficient routing with optimum device utilization and high performance
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