參數(shù)資料
型號: EPCS1SI8
廠商: Altera
文件頁數(shù): 11/40頁
文件大小: 0K
描述: IC CONFIG DEVICE 1MBIT 8-SOIC
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 100
系列: EPCS
可編程類型: 系統(tǒng)內(nèi)可編程
存儲(chǔ)容量: 1Mb
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
產(chǎn)品目錄頁面: 604 (CN2011-ZH PDF)
其它名稱: 544-1241-5
EPCS Device Memory Access
Page 19
Serial Configuration (EPCS) Devices Datasheet
January 2014
Altera Corporation
You can read the status register at any time, even during a write or erase cycle is in
progress. When one of these cycles is in progress, you can check the write in progress
bit (bit 0 of the status register) before sending a new operation to the device. The
device can also read the status register continuously, as shown in Figure 9.
Table 12. Block Protection Bits in the EPCS64 Devices
Status Register
Content
Memory Content
BP2
Bit
BP1
Bit
BP0
Bit
Protected Area
Unprotected Area
0
None
All sectors (128 sectors: 0 to 127)
0
1
Upper 64th (2 sectors: 126 and 127)
Lower 63/64ths (126 sectors: 0 to 125)
0
1
0
Upper 32nd (4 sectors: 124 to 127)
Lower 31/32nds (124 sectors: 0 to 123)
0
1
Upper sixteenth (8 sectors: 120 to 127)
Lower 15/16ths (120 sectors: 0 to 119)
1
0
Upper eighth (16 sectors: 112 to 127)
Lower seven-eights (112 sectors: 0 to 111)
1
0
1
Upper quarter (32 sectors: 96 to 127)
Lower three-quarters (96 sectors: 0 to 95)
1
0
Upper half (64 sectors: 64 to 127)
Lower half (64 sectors: 0 to 63)
1
All sectors (128 sectors: 0 to 127)
None
Table 13. Block Protection Bits in the EPCS128 Device
Status Register
Content
Memory Content
BP2
Bit
BP1
Bit
BP0
Bit
Protected Area
Unprotected Area
000
None
All sectors (64 sectors—0 to 63)
001
Upper 64th (1 sector—63)
Lower 63/64ths (63 sectors—0 to 62)
010
Upper 32nd (2 sectors—62 to 63)
Lower 31/32nds (62 sectors—0 to 61)
011
Upper 16th (4 sectors—60 to 63)
Lower 15/16ths (60 sectors—0 to 59)
100
Upper 8th (8 sectors—56 to 63)
Lower seven-eighths (56 sectors—0 to 55)
101
Upper quarter (16 sectors—48 to 63)
Lower three-quarters (48 sectors—0 to 47)
110
Upper half (32 sectors—32 to 63)
Lower half (32 sectors—0 to 31)
111
All sectors (64 sectors—0 to 63)
None
Figure 9. Read Status Operation Timing Diagram
nCS
DCLK
ASDI
DATA
0
1
2
3
4
5
6
7
8
9
101112131415
765432107
2107
6543
Operation Code
MSB
Status Register Out
High Impedance
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