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鍨嬭櫉(h脿o)锛� EP7312-IR-90
寤犲晢锛� Cirrus Logic Inc
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鎸暕鍣ㄥ瀷锛� 澶栭儴
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閰嶇敤锛� 598-1209-ND - KIT DEVELOPMENT EP73XX ARM7
鍏跺畠鍚嶇ū锛� 598-1244
DS508F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
15
EP7312
High-Performance, Low-Power System on Chip
Timings
Timing Diagram Conventions
This data sheet contains timing diagrams. The following key explains the components used in these diagrams. Any variations are
clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated.
Timing Conditions
Unless specified otherwise, the following conditions are true for all timing measurements. All characteristics are specified at
VDDIO = 3.1 - 3.5 V and VSS = 0 V over an operating temperature of -40C to +85C. Pin loadings is 50 pF. The timing values are
referenced to 1/2 VDD.
Cl o c k
Hi g h
t o
L o w
H i gh / L ow
t o
H i g h
B u s
C h an ge
Bu s
Va l i d
U n de f i ne d/ I n v a l i d
V a l i d
B u s
to
T r i s ta te
B u s / S i gn al O m i s s i on
Figure 2. Legend for Timing Diagrams
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
PIC16LF873A-I/ML IC PIC MCU FLASH 4KX14 28QFN
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AT87C51RC2-3CSUL IC 8051 MCU 32K OTP 30MHZ 40DIP
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EP7312-IV 鍔熻兘鎻忚堪:IC ARM720T MCU 74MHZ 208-LQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰帶鍒跺櫒锛� 绯诲垪:EP7 妯�(bi膩o)婧�(zh菙n)鍖呰:1,500 绯诲垪:AVR® ATtiny 鏍稿績铏曠悊鍣�:AVR 鑺珨灏哄:8-浣� 閫熷害:16MHz 閫i€氭€�:I²C锛孡IN锛孲PI锛孶ART/USART锛孶SI 澶栧湇瑷�(sh猫)鍌�:娆犲妾㈡脯/寰�(f霉)浣�锛孭OR锛孭WM锛屾韩搴﹀偝鎰熷櫒锛學DT 杓稿叆/杓稿嚭鏁�(sh霉):16 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲�:8KB锛�4K x 16锛� 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨�:闁冨瓨 EEPROM 澶у皬:512 x 8 RAM 瀹归噺:512 x 8 闆诲 - 闆绘簮 (Vcc/Vdd):2.7 V ~ 5.5 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:A/D 11x10b 鎸暕鍣ㄥ瀷:鍏�(n猫i)閮� 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:20-SOIC锛�0.295"锛�7.50mm 瀵級 鍖呰:甯跺嵎 (TR)
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EP7312-IV-C 鍒堕€犲晢:CIRRUS 鍒堕€犲晢鍏ㄧū:Cirrus Logic 鍔熻兘鎻忚堪:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE