參數(shù)資料
型號： EP4SGX70HF35I3N
廠商： Altera
文件頁數(shù)： 62/82頁
文件大?。?/td> 0K
描述： IC STRATIX IV FPGA 70K 1152FBGA
產(chǎn)品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 3
系列： Stratix® IV GX
LAB/CLB數(shù)： 2904
邏輯元件/單元數(shù)： 72600
RAM 位總計： 7564880
輸入/輸出數(shù)： 488
電源電壓： 0.87 V ~ 0.93 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 1152-BBGA
供應商設備封裝： 1152-FBGA（27x27）
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–57
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Table 1–43 lists the DPA lock time specifications for Stratix IV ES devices.
Figure 1–4 shows the DPA lock time specifications with DPA PLL calibration enabled.
Table 1–43. DPA Lock Time Specifications—Stratix IV ES Devices Only (1), (2), (3)
Standard
Training Pattern
Number of Data
Transitions in
one repetition
of training
pattern
Number of
repetitions
per 256
data
transitions
Condition
Maximum
SPI-4
00000000001111111111
2
128
without DPA PLL
calibration
256 data transitions
with DPA PLL
calibration
3x256 data transitions +
2x96 slow clock cycles (5)
Parallel Rapid
I/O
00001111
2
128
without DPA PLL
calibration
256 data transitions
with DPA PLL
calibration
3x256 data transitions +
2x96 slow clock cycles (5)
10010000
4
64
without DPA PLL
calibration
256 data transitions
with DPA PLL
calibration
3x256 data transitions +
2x96 slow clock cycles (5)
Miscellaneous
10101010
8
32
without DPA PLL
calibration
256 data transitions
with DPA PLL
calibration
3x256 data transitions +
2x96 slow clock cycles (5)
01010101
8
32
without DPA PLL
calibration
256 data transitions
with DPA PLL
calibration
3x256 data transitions +
2x96 slow clock cycles (5)
Notes to Table 1–43
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time applies to commercial, industrial, and military speed grades.
(4) This is the number of repetition for the stated training pattern to achieve 256 data transitions.
(5) Slow clock = Data rate (Mbps)/Deserialization factor.
Figure 1–4. DPA Lock Time Specification with DPA PLL Calibration Enabled
rx_dpa_locked
rx_reset
DPA Lock Time
256 data
transitions
96 slow
clock cycles
256 data
transitions
256 data
transitions
96 slow
clock cycles
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參數(shù)描述
EP4SGX70HF35I4 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 2904 LABs 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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EP4-SPR-BULK 功能描述:SONIC DEFENDER SMALL CLEAR RoHS:是 類別:音頻產(chǎn)品 >> 配件 系列:EarPro 標準包裝:1 系列:- 附件類型:墊圈 材質:氯丁橡膠 顏色:黑 適用于相關產(chǎn)品:Sonalert? 信號設備 其它名稱:458-1048
EP5 制造商:Datak Corporation 功能描述:
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