參數(shù)資料
型號(hào): EP4SGX70HF35I3
廠商: Altera
文件頁數(shù): 27/82頁
文件大?。?/td> 0K
描述: IC STRATIX IV FPGA 70K 1152FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 3
系列: Stratix® IV GX
LAB/CLB數(shù): 2904
邏輯元件/單元數(shù): 72600
RAM 位總計(jì): 7564880
輸入/輸出數(shù): 488
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1152-BBGA
供應(yīng)商設(shè)備封裝: 1152-FBGA(27x27)
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–25
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Figure 1–1 shows the top-to-bottom AC gain curve for equalization settings 0 to 15.
Table 1–24 lists the Stratix IV GT transceiver specifications.
Figure 1–1. AC Gain Curves for Equalization Settings 0 to 15 (Bottom to Top)
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 1 of 8)
Symbol/
Description
Conditions
–1 Industrial Speed
Grade
–2 Industrial Speed
Grade
–3 Industrial Speed
Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Reference Clock
Supported I/O
Standards
1.2 V PCML, 1.4 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL (3), LVDS
Input frequency
from REFCLK input
pins
50
706.25
50
706.25
50
706.25
MHz
Phase frequency
detector (CMU PLL
and receiver CDR)
50
425
50
425
50
425
MHz
Absolute VMAX for a
REFCLK
pin
1.6
1.6
1.6
V
Operational VMAX for
a REFCLK pin
1.5
1.5
1.5
V
Absolute VMIN for a
REFCLK
pin
-0.3
-0.3
-0.3
V
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