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    參數(shù)資料
    型號(hào): EP4SGX180HF35C3N
    廠商: Altera
    文件頁(yè)數(shù): 33/82頁(yè)
    文件大?。?/td> 0K
    描述: IC STRATIX IV FPGA 180K 1152FBGA
    產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
    標(biāo)準(zhǔn)包裝: 3
    系列: Stratix® IV GX
    LAB/CLB數(shù): 7030
    邏輯元件/單元數(shù): 175750
    RAM 位總計(jì): 13954048
    輸入/輸出數(shù): 564
    電源電壓: 0.87 V ~ 0.93 V
    安裝類(lèi)型: 表面貼裝
    工作溫度: 0°C ~ 85°C
    封裝/外殼: 1152-BBGA
    供應(yīng)商設(shè)備封裝: 1152-FBGA(27x27)
    Chapter 1: DC and Switching Characteristics for Stratix IV Devices
    1–31
    Switching Characteristics
    March 2014
    Altera Corporation
    Stratix IV Device Handbook
    Volume 4: Device Datasheet and Addendum
    Inter-transceiver
    block skew in Basic
    (PMA Direct) ×N
    mode (14)
    N < 18 channels
    located across
    three
    transceiver
    blocks with the
    source CMU
    PLL located in
    the center
    transceiver
    block
    400
    400
    400
    ps
    N
    18
    channels
    located across
    four transceiver
    blocks with the
    source CMU
    PLL located in
    one of the two
    center
    transceiver
    blocks
    650
    650
    650
    ps
    CMU PLL0 and CMU PLL1
    Supported data
    range
    600
    11300
    600
    10312.5
    600
    8500
    Mbps
    CMU PLL lock time
    from
    pll_powerdown
    de-assertion
    100
    100
    100
    s
    ATX PLL (6G)
    Supported Data
    Range
    /L = 1
    4800-5400 and
    6000-6500
    4800-5400 and
    6000-6500
    4800-5400 and
    6000-6500
    Mbps
    /L = 2
    2400-2700 and
    3000-3250
    2400-2700 and
    3000-3250
    2400-2700 and
    3000-3250
    Mbps
    /L = 4
    1200-1350 and
    1500-1625
    1200-1350 and
    1500-1625
    1200-1350 and
    1500-1625
    Mbps
    ATX PLL (10G)
    Supported Data
    Range
    9900
    11300
    9900
    10312.5
    Mbps
    Transceiver-FPGA Fabric Interface
    Interface speed
    (non-PMA Direct)
    25
    325
    25
    325
    25
    265.625
    MHz
    Interface speed
    (PMA Direct)
    50
    325
    50
    325
    50
    325
    MHz
    Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 7 of 8)
    Symbol/
    Description
    Conditions
    –1 Industrial Speed
    Grade
    –2 Industrial Speed
    Grade
    –3 Industrial Speed
    Grade
    Unit
    Min
    Typ
    Max
    Min
    Typ
    Max
    Min
    Typ
    Max
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    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    EP4SGX180HF35C4 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Stratix IV GX 7030 LABs 564 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
    EP4SGX180HF35C4N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Stratix IV GX 7030 LABs 564 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
    EP4SGX180HF35I3 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Stratix IV GX 7030 LABs 564 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
    EP4SGX180HF35I3N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Stratix IV GX 7030 LABs 564 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
    EP4SGX180HF35I4 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Stratix IV GX 7030 LABs 564 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256