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    參數(shù)資料
    型號(hào)： EP4SGX110FF35I4N
    廠商： Altera
    文件頁(yè)數(shù)： 10/82頁(yè)
    文件大?。?/td> 0K
    描述： IC STRATIX IV FPGA 110K 1152FBGA
    產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
    標(biāo)準(zhǔn)包裝： 3
    系列： Stratix® IV GX
    LAB/CLB數(shù)： 4224
    邏輯元件/單元數(shù)： 105600
    RAM 位總計(jì)： 9793536
    輸入/輸出數(shù)： 372
    電源電壓： 0.87 V ~ 0.93 V
    安裝類型： 表面貼裝
    工作溫度： -40°C ~ 100°C
    封裝/外殼： 1152-BBGA
    供應(yīng)商設(shè)備封裝： 1152-FBGA（27x27）
    Chapter 1: DC and Switching Characteristics for Stratix IV Devices
    1–10
    Electrical Characteristics
    March 2014
    Altera Corporation
    Stratix IV Device Handbook
    Volume 4: Device Datasheet and Addendum
    OCT calibration is automatically performed at power-up for OCT-enabled I/Os.
    Table 1–13 lists OCT variation with temperature and voltage after power-up
    calibration. Use Table 1–13 to determine the OCT variation after power-up calibration
    and Equation 1–1 to determine the OCT variation without re-calibration.
    Table 1–13 lists the OCT variation after the power-up calibration.
    Pin Capacitance
    Table 1–14 lists the Stratix IV device family pin capacitance.
    Equation 1–1. OCT Variation Without Re-Calibration (1), (2), (3), (4), (5), (6)
    (1) The ROCT value calculated from Equation 1–1 shows the range of OCT resistance with the variation of temperature
    and VCCIO.
    (2) RSCAL is the OCT resistance value at power-up.
    (3)
    T is the variation of temperature with respect to the temperature at power-up.
    (4)
    V is the variation of voltage with respect to the V
    CCIO at power-up.
    (5) dR/dT is the percentage change of RSCAL with temperature.
    (6) dR/dV is the percentage change of RSCAL with voltage.
    Table 1–13. OCT Variation after Power-Up Calibration (1)
    Symbol
    Description
    VCCIO (V)
    Typical
    Unit
    dR/dV
    OCT variation with voltage without
    re-calibration
    3.0
    0.0297
    %/mV
    2.5
    0.0344
    1.8
    0.0499
    1.5
    0.0744
    1.2
    0.1241
    dR/dT
    OCT variation with temperature
    without re-calibration
    3.0
    0.189
    %/°C
    2.5
    0.208
    1.8
    0.266
    1.5
    0.273
    1.2
    0.317
    Note to Table 1–13:
    (1) Valid for VCCIO range of ±5% and temperature range of 0° to 85°C.
    ROCT
    RSCAL 1
    dR
    dT
    -------
    T
    dR
    dV
    -------
    V
    +
    =
    Table 1–14. Pin Capacitance for Stratix IV Devices (Part 1 of 2)
    Symbol
    Description
    Value
    Unit
    CIOTB
    Input capacitance on the top and bottom I/O pins
    4
    pF
    CIOLR
    Input capacitance on the left and right I/O pins
    4
    pF
    CCLKTB
    Input capacitance on the top and bottom non-dedicated clock input pins
    4
    pF
    CCLKLR
    Input capacitance on the left and right non-dedicated clock input pins
    4
    pF
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    參數(shù)描述
    EP4SGX110HF35C2 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix IV GX 4224 LABs 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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    EP4SGX110HF35C2NGA 制造商:Altera Corporation 功能描述:
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    EP4SGX110HF35C3N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix IV GX 4224 LABs 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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