- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4299 > EP4S100G4F45I1N (Altera)IC STRATIX IV FPGA 360K 1932FBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | EP4S100G4F45I1N |
| 廠商： | Altera |
| 文件頁數(shù)： | 18/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC STRATIX IV FPGA 360K 1932FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 3 |
| 系列： | STRATIX® IV GT |
| LAB/CLB數(shù)： | 14144 |
| 邏輯元件/單元數(shù)： | 353600 |
| RAM 位總計(jì)： | 23105536 |
| 輸入/輸出數(shù)： | 781 |
| 電源電壓： | 0.92 V ~ 0.98 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 1932-BBGA |
| 供應(yīng)商設(shè)備封裝： | 1932-FBGA（45x45） |
Chapter 1: Overview for the Stratix IV Device Family
1–5
Feature Summary
September 2012
Altera Corporation
Stratix IV GT Devices
Stratix IV GT devices provide up to 48 CDR-based transceiver channels per device:
■
Thirty-two out of the 48 transceiver channels have dedicated PCS and PMA
circuitry and support data rates between 600 Mbps and 11.3 Gbps
■
The remaining 16 transceiver channels have dedicated PMA-only circuitry and
support data rates between 600 Mbps and 6.5 Gbps
1 The actual number of transceiver channels per device varies with device selection. For
more information about the exact transceiver count in each device, refer to Table 1–7
1 For more information about Stratix IV GT devices and transceiver architecture, refer
to the Transceiver Architecture in Stratix IV Devices chapter.
Figure 1–3 shows a high-level Stratix IV GT chip view.
Figure 1–3. Stratix IV GT Chip View (1)
Note to Figure 1–3:
(1) Resource counts vary with device selection, package selection, or both.
General Purpose
I/O and Memory
Interface
600 Mbps-11.3 Gbps CDR-based Transceiver
General Purpose I/O and up to 1.6 Gbps
LVDS interface with DPA and Soft-CDR
PCI
Express
Hard
IP
Bloc
k
PCI
Express
Hard
IP
Bloc
k
PCI
Express
Hard
IP
Bloc
k
PCI
Express
Hard
IP
Bloc
k
T
ranscei
v
er
Bloc
k
T
ranscei
v
er
Bloc
k
T
ranscei
v
er
Bloc
k
T
ranscei
v
er
Bloc
k
General Purpose
I/O and Memory
Interface
PLL
General Purpose
I/O and Memory
Interface
General Purpose
I/O and Memory
Interface
PLL
FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
Transceiver Block
General Purpose I/O and
High-Speed LVDS I/O
with DPA and Soft CDR
Gener
al
P
u
rpose
I/O
and
High-Speed
L
V
DS
I/O
w
ith
DP
A
and
Soft
CDR
PLL
Gener
al
P
u
rpose
I/O
and
High-Speed
L
V
DS
I/O
w
ith
DP
A
and
Soft
CDR
Gener
al
P
u
rpose
I/O
and
High-Speed
L
V
DS
I/O
w
ith
DP
A
and
Soft
CDR
Gener
al
P
u
rpose
I/O
and
High-Speed
L
V
DS
I/O
w
ith
DP
A
and
Soft
CDR
T
ranscei
v
er
Bloc
k
T
ranscei
v
er
Bloc
k
T
ranscei
v
er
Bloc
k
T
ranscei
v
er
Bloc
k
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。