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參數(shù)資料
| 型號： | EP4S100G3F45I3N |
| 廠商： | Altera |
| 文件頁數(shù)： | 14/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC STRATIX IV FPGA 290K 1932FBGA |
| 產(chǎn)品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 3 |
| 系列： | STRATIX® IV GT |
| LAB/CLB數(shù)： | 11648 |
| 邏輯元件/單元數(shù)： | 291200 |
| RAM 位總計： | 17661952 |
| 輸入/輸出數(shù)： | 781 |
| 電源電壓： | 0.92 V ~ 0.98 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 1932-BBGA |
| 供應商設備封裝： | 1932-FBGA（45x45） |
Chapter 1: Overview for the Stratix IV Device Family
1–21
Ordering Information
September 2012
Altera Corporation
November 2009
3.0
■ Updated the “Stratix IV Device Family Overview”, “Feature Summary”, “Stratix IV GT
Devices”, “High-Speed Transceiver Features”, “FPGA Fabric and I/O Features”, “Highest
Aggregate Data Bandwidth”, “System Integration”, and “Integrated Software Platform”
sections.
■ Added Table 1–3, Table 1–6, and Table 1–9.
■ Updated Table 1–1, Table 1–2, Table 1–4, Table 1–5, Table 1–7, and Table 1–8.
■ Updated Figure 1–3, Figure 1–4, and Figure 1–5.
■ Minor text edits.
June 2009
2.4
■ Updated Table 1–1.
■ Minor text edits.
April 2009
2.3
■ Added Table 1–5, Table 1–6, and Figure 1–3.
■ Updated Figure 1–5.
■ Updated Table 1–1, Table 1–2, Table 1–3, and Table 1–4.
■ Updated “Introduction”, “Feature Summary”, “Stratix IV GX Devices”, “Stratix IV GT
Devices”, “Architecture Features”, and “FPGA Fabric and I/O Features”
March 2009
2.2
■ Updated “Feature Summary”, “Stratix IV GX Devices”, “Stratix IV E Device”, “Stratix IV
GT Devices”, “Signal Integrity”
■ Removed Tables 1-5 and 1-6
■ Updated Figure 1–4
March 2009
2.1
■ Updated “Introduction”, “Feature Summary”, “Stratix IV Device Diagnostic Features”,
“Signal Integrity”, “Clock Networks”,“High-Speed Differential I/O with DPA and Soft-
CDR”, “System Integration”, and “Ordering Information” sections.
■ Added “Stratix IV GT 100G Devices” and “Stratix IV GT 100G Transceiver Bandwidth”
sections.
■ Updated Table 1–1, Table 1–2, Table 1–3, and Table 1–4.
■ Added Table 1–5 and Table 1–6.
■ Updated Figure 1–3 and Figure 1–4.
■ Added Figure 1–5.
■ Removed “Referenced Documents” section.
November 2008
2.0
■ Updated “Feature Summary” on page 1–1.
■ Updated “Stratix IV Device Diagnostic Features” on page 1–7.
■ Updated “FPGA Fabric and I/O Features” on page 1–8.
■ Updated Table 1–1.
■ Updated Table 1–2.
■ Updated “Table 1–5 shows the total number of transceivers available in the Stratix IV GT
Device.” on page 1–15.
July 2008
1.1
Revised “Introduction”.
May 2008
1.0
Initial release.
Table 1–10. Document Revision History (Part 2 of 2)
Date
Version
Changes
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EP4S100G4F45I1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 14144 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S100G4F45I1N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 14144 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S100G4F45I2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 14144 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S100G4F45I2N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 14144 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S100G4F45I3 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 14144 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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